Array
(
[id] => 5571317
[patent_doc_number] => 20090254696
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-08
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/417704
[patent_app_country] => US
[patent_app_date] => 2009-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 36523
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0254/20090254696.pdf
[firstpage_image] =>[orig_patent_app_number] => 12417704
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/417704 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT | Apr 2, 2009 | Abandoned |
Array
(
[id] => 5375861
[patent_doc_number] => 20090313422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-17
[patent_title] => 'FLASH MEMORY CONTROL APPARATUS HAVING SEQUENTIAL WRITING PROCEDURE AND METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/327055
[patent_app_country] => US
[patent_app_date] => 2008-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2887
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0313/20090313422.pdf
[firstpage_image] =>[orig_patent_app_number] => 12327055
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/327055 | FLASH MEMORY CONTROL APPARATUS HAVING SEQUENTIAL WRITING PROCEDURE AND METHOD THEREOF | Dec 2, 2008 | Abandoned |
Array
(
[id] => 6647543
[patent_doc_number] => 20100037003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'FLASH MEMORY CONTROL APPARATUS HAVING SIGNAL-CONVERTING MODULE'
[patent_app_type] => utility
[patent_app_number] => 12/327065
[patent_app_country] => US
[patent_app_date] => 2008-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2548
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20100037003.pdf
[firstpage_image] =>[orig_patent_app_number] => 12327065
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/327065 | FLASH MEMORY CONTROL APPARATUS HAVING SIGNAL-CONVERTING MODULE | Dec 2, 2008 | Abandoned |
Array
(
[id] => 5516639
[patent_doc_number] => 20090216946
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'RAID1 SYSTEM AND READING METHOD FOR ENHANCING READ PERFORMANCE'
[patent_app_type] => utility
[patent_app_number] => 12/126913
[patent_app_country] => US
[patent_app_date] => 2008-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4285
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20090216946.pdf
[firstpage_image] =>[orig_patent_app_number] => 12126913
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/126913 | RAID1 SYSTEM AND READING METHOD FOR ENHANCING READ PERFORMANCE | May 24, 2008 | Abandoned |
Array
(
[id] => 5475837
[patent_doc_number] => 20090249003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'METHOD AND SYSTEM FOR MULTIPLEXING CONCATENATED STORAGE DISK ARRAYS TO FORM A RULES-BASED ARRAY OF DISKS'
[patent_app_type] => utility
[patent_app_number] => 12/055475
[patent_app_country] => US
[patent_app_date] => 2008-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4308
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20090249003.pdf
[firstpage_image] =>[orig_patent_app_number] => 12055475
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/055475 | METHOD AND SYSTEM FOR MULTIPLEXING CONCATENATED STORAGE DISK ARRAYS TO FORM A RULES-BASED ARRAY OF DISKS | Mar 25, 2008 | Abandoned |
Array
(
[id] => 4722183
[patent_doc_number] => 20080244135
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'Memory Controller and Method For Controlling Access to a Memory, as Well as System Comprising a Memory Controller'
[patent_app_type] => utility
[patent_app_number] => 11/913660
[patent_app_country] => US
[patent_app_date] => 2006-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 16820
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0244/20080244135.pdf
[firstpage_image] =>[orig_patent_app_number] => 11913660
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/913660 | Memory Controller and Method For Controlling Access to a Memory, as Well as System Comprising a Memory Controller | Apr 30, 2006 | Abandoned |