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Brian Bembenick

Examiner (ID: 11143)

Most Active Art Unit
1209
Art Unit(s)
1209, 1616
Total Applications
444
Issued Applications
312
Pending Applications
26
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18812254 [patent_doc_number] => 20230386591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => NON-VOLATILE MEMORY CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/448152 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448152
NON-VOLATILE MEMORY CIRCUIT AND METHOD Aug 9, 2023 Pending
Array ( [id] => 18812199 [patent_doc_number] => 20230386536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MEMORY DEVICE WITH SOURCE LINE CONTROL [patent_app_type] => utility [patent_app_number] => 18/232542 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232542
MEMORY DEVICE WITH SOURCE LINE CONTROL Aug 9, 2023 Pending
Array ( [id] => 18820819 [patent_doc_number] => 20230395160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => FLOATING DATA LINE CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/362549 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362549
FLOATING DATA LINE CIRCUIT AND METHOD Jul 30, 2023 Pending
Array ( [id] => 18848447 [patent_doc_number] => 20230410851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL [patent_app_type] => utility [patent_app_number] => 18/362270 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362270 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362270
HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL Jul 30, 2023 Pending
Array ( [id] => 19370318 [patent_doc_number] => 12062408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Switches to reduce routing rails of memory system [patent_app_type] => utility [patent_app_number] => 18/361542 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8387 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361542
Switches to reduce routing rails of memory system Jul 27, 2023 Issued
Array ( [id] => 18743072 [patent_doc_number] => 20230352060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => CIRCUIT MODULE WITH IMPROVED LINE LOAD [patent_app_type] => utility [patent_app_number] => 18/221111 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221111
Circuit module with improved line load Jul 11, 2023 Issued
Array ( [id] => 18731392 [patent_doc_number] => 20230345700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => Semiconductor Memory Device Having an Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 18/216359 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216359 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216359
Semiconductor Memory Device Having an Electrically Floating Body Transistor Jun 28, 2023 Pending
Array ( [id] => 19427950 [patent_doc_number] => 12087378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Bit selection for power reduction in stacking structure during memory programming [patent_app_type] => utility [patent_app_number] => 18/318000 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318000 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318000
Bit selection for power reduction in stacking structure during memory programming May 15, 2023 Issued
Array ( [id] => 19213471 [patent_doc_number] => 12002543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Memory device for supporting new command input scheme and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/299440 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 17654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/299440
Memory device for supporting new command input scheme and method of operating the same Apr 11, 2023 Issued
Array ( [id] => 19399482 [patent_doc_number] => 12073867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/178934 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178934 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178934
Memory device Mar 5, 2023 Issued
Array ( [id] => 18423654 [patent_doc_number] => 20230178118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => MEMORY CIRCUIT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/163146 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/163146
Memory circuit architecture Jan 31, 2023 Issued
Array ( [id] => 18890800 [patent_doc_number] => 11869577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Decoding architecture for memory devices [patent_app_type] => utility [patent_app_number] => 18/100802 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 23726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100802 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100802
Decoding architecture for memory devices Jan 23, 2023 Issued
Array ( [id] => 18379468 [patent_doc_number] => 20230154557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 18/155925 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155925 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155925
Memory circuit and method of operating same Jan 17, 2023 Issued
Array ( [id] => 18408672 [patent_doc_number] => 20230170025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/153007 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153007
Non-volatile memory device and programming method thereof Jan 10, 2023 Issued
Array ( [id] => 18890788 [patent_doc_number] => 11869565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Read algorithm for memory device [patent_app_type] => utility [patent_app_number] => 18/056516 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18056516 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/056516
Read algorithm for memory device Nov 16, 2022 Issued
Array ( [id] => 18688156 [patent_doc_number] => 11783899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/973549 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 39 [patent_no_of_words] => 19215 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/973549
Semiconductor memory device Oct 25, 2022 Issued
Array ( [id] => 18196179 [patent_doc_number] => 20230049698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/973823 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/973823
Memory device and operating method thereof Oct 25, 2022 Issued
Array ( [id] => 18162378 [patent_doc_number] => 20230028971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/959098 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959098
Semiconductor memory device Oct 2, 2022 Issued
Array ( [id] => 18334978 [patent_doc_number] => 20230126926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => EDGELESS MEMORY CLUSTERS [patent_app_type] => utility [patent_app_number] => 17/950895 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950895 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950895
Edgeless memory clusters Sep 21, 2022 Issued
Array ( [id] => 18857007 [patent_doc_number] => 11854598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Self refresh of memory cell [patent_app_type] => utility [patent_app_number] => 17/940760 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940760
Self refresh of memory cell Sep 7, 2022 Issued
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