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Gary F Paumen

Examiner (ID: 12182)

Most Active Art Unit
2833
Art Unit(s)
2833, 2834, 2899, 3202, 2832, 0
Total Applications
6973
Issued Applications
5993
Pending Applications
249
Abandoned Applications
705

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2842964 [patent_doc_number] => 05175833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Apparatus for determining relative position of a cache memory in a cache memory array' [patent_app_type] => 1 [patent_app_number] => 7/534753 [patent_app_country] => US [patent_app_date] => 1990-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5299 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175833.pdf [firstpage_image] =>[orig_patent_app_number] => 534753 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/534753
Apparatus for determining relative position of a cache memory in a cache memory array Jun 6, 1990 Issued
Array ( [id] => 2952603 [patent_doc_number] => 05181017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-19 [patent_title] => 'Adaptive routing in a parallel computing system' [patent_app_type] => 1 [patent_app_number] => 7/386521 [patent_app_country] => US [patent_app_date] => 1989-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5779 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/181/05181017.pdf [firstpage_image] =>[orig_patent_app_number] => 386521 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/386521
Adaptive routing in a parallel computing system Jul 26, 1989 Issued
Array ( [id] => 2842945 [patent_doc_number] => 05175832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Modular memory employing varying number of imput shift register stages' [patent_app_type] => 1 [patent_app_number] => 7/355922 [patent_app_country] => US [patent_app_date] => 1989-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175832.pdf [firstpage_image] =>[orig_patent_app_number] => 355922 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/355922
Modular memory employing varying number of imput shift register stages May 22, 1989 Issued
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