Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3849245
[patent_doc_number] => 05761438
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Apparatus for measuring the amount of traffic of a network at a predetermined timing and compressing data in the packet without changing the size of the packet'
[patent_app_type] => 1
[patent_app_number] => 8/923981
[patent_app_country] => US
[patent_app_date] => 1997-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 7912
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[patent_words_short_claim] => 102
[patent_maintenance] => 1
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[pdf_file] => patents/05/761/05761438.pdf
[firstpage_image] =>[orig_patent_app_number] => 923981
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/923981 | Apparatus for measuring the amount of traffic of a network at a predetermined timing and compressing data in the packet without changing the size of the packet | Sep 4, 1997 | Issued |
Array
(
[id] => 3797570
[patent_doc_number] => 05758194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Communication apparatus for handling networks with different transmission protocols by stripping or adding data to the data stream in the application layer'
[patent_app_type] => 1
[patent_app_number] => 8/887525
[patent_app_country] => US
[patent_app_date] => 1997-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3063
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 187
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/758/05758194.pdf
[firstpage_image] =>[orig_patent_app_number] => 887525
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/887525 | Communication apparatus for handling networks with different transmission protocols by stripping or adding data to the data stream in the application layer | Jul 2, 1997 | Issued |
Array
(
[id] => 3878813
[patent_doc_number] => 05797036
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Apparatus which prepares a master map portraying location of devices relative to bus interface circuits and copying the pertinent portion of the master map to each bus interface circuits'
[patent_app_type] => 1
[patent_app_number] => 8/840429
[patent_app_country] => US
[patent_app_date] => 1997-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 3884
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[pdf_file] => patents/05/797/05797036.pdf
[firstpage_image] =>[orig_patent_app_number] => 840429
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840429 | Apparatus which prepares a master map portraying location of devices relative to bus interface circuits and copying the pertinent portion of the master map to each bus interface circuits | Apr 28, 1997 | Issued |
Array
(
[id] => 3634250
[patent_doc_number] => 05689671
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-18
[patent_title] => 'System for reducing quantity of data transmitted to a user unit by transmitting only an identifier which points to pre-stored information in the user unit'
[patent_app_type] => 1
[patent_app_number] => 8/764229
[patent_app_country] => US
[patent_app_date] => 1996-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4878
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[pdf_file] => patents/05/689/05689671.pdf
[firstpage_image] =>[orig_patent_app_number] => 764229
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764229 | System for reducing quantity of data transmitted to a user unit by transmitting only an identifier which points to pre-stored information in the user unit | Dec 12, 1996 | Issued |
Array
(
[id] => 3795125
[patent_doc_number] => 05809330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Conflict free PC in which only the I/O address of internal device is change when it is determined that the I/O address is overlap by expansion device'
[patent_app_type] => 1
[patent_app_number] => 8/720273
[patent_app_country] => US
[patent_app_date] => 1996-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 12611
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[pdf_file] => patents/05/809/05809330.pdf
[firstpage_image] =>[orig_patent_app_number] => 720273
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/720273 | Conflict free PC in which only the I/O address of internal device is change when it is determined that the I/O address is overlap by expansion device | Sep 25, 1996 | Issued |
Array
(
[id] => 3837465
[patent_doc_number] => 05790896
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Apparatus for a testing system with a plurality of first connection having a structural characteristic and a plurality of second connection having a different structural characteristic than the first connection'
[patent_app_type] => 1
[patent_app_number] => 8/682902
[patent_app_country] => US
[patent_app_date] => 1996-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3284
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[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/790/05790896.pdf
[firstpage_image] =>[orig_patent_app_number] => 682902
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/682902 | Apparatus for a testing system with a plurality of first connection having a structural characteristic and a plurality of second connection having a different structural characteristic than the first connection | Jun 23, 1996 | Issued |
08/634952 | INTER-NETWORK COMMUNICATIONS GATEWAY AND DATA TRANSMISSION PROTOCOL | Apr 18, 1996 | Abandoned |
Array
(
[id] => 3873292
[patent_doc_number] => 05768620
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Variable timeout method in a missing-interrupt-handler for I/O requests issued by the same operating system'
[patent_app_type] => 1
[patent_app_number] => 8/631689
[patent_app_country] => US
[patent_app_date] => 1996-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 12021
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/768/05768620.pdf
[firstpage_image] =>[orig_patent_app_number] => 631689
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/631689 | Variable timeout method in a missing-interrupt-handler for I/O requests issued by the same operating system | Apr 8, 1996 | Issued |
Array
(
[id] => 3898654
[patent_doc_number] => 05805931
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols'
[patent_app_type] => 1
[patent_app_number] => 8/598896
[patent_app_country] => US
[patent_app_date] => 1996-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 29
[patent_no_of_words] => 9653
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[pdf_file] => patents/05/805/05805931.pdf
[firstpage_image] =>[orig_patent_app_number] => 598896
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/598896 | Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols | Feb 8, 1996 | Issued |
Array
(
[id] => 3759677
[patent_doc_number] => 05754890
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'System for automatic identification of a computer data entry device interface type using a transistor to sense the voltage generated by the interface and output a matching voltage level'
[patent_app_type] => 1
[patent_app_number] => 8/595345
[patent_app_country] => US
[patent_app_date] => 1996-02-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/754/05754890.pdf
[firstpage_image] =>[orig_patent_app_number] => 595345
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/595345 | System for automatic identification of a computer data entry device interface type using a transistor to sense the voltage generated by the interface and output a matching voltage level | Jan 31, 1996 | Issued |
Array
(
[id] => 3837399
[patent_doc_number] => 05790891
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Synchronizing unit having two registers serially connected to one clocked elements and a latch unit for alternately activating the registers in accordance to clock signals'
[patent_app_type] => 1
[patent_app_number] => 8/585335
[patent_app_country] => US
[patent_app_date] => 1996-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2706
[patent_no_of_claims] => 8
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/790/05790891.pdf
[firstpage_image] =>[orig_patent_app_number] => 585335
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/585335 | Synchronizing unit having two registers serially connected to one clocked elements and a latch unit for alternately activating the registers in accordance to clock signals | Jan 10, 1996 | Issued |
Array
(
[id] => 3634207
[patent_doc_number] => 05615402
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch'
[patent_app_type] => 1
[patent_app_number] => 8/572584
[patent_app_country] => US
[patent_app_date] => 1995-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 18068
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[pdf_file] => patents/05/615/05615402.pdf
[firstpage_image] =>[orig_patent_app_number] => 572584
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/572584 | Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch | Dec 13, 1995 | Issued |
Array
(
[id] => 3873237
[patent_doc_number] => 05768616
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Apparatus for detecting electro-magnetic stylus signals by inducing current into a plurality of sensor coils using signals transmitted by the tranmitter coil of the stylus'
[patent_app_type] => 1
[patent_app_number] => 8/573211
[patent_app_country] => US
[patent_app_date] => 1995-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
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[pdf_file] => patents/05/768/05768616.pdf
[firstpage_image] =>[orig_patent_app_number] => 573211
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/573211 | Apparatus for detecting electro-magnetic stylus signals by inducing current into a plurality of sensor coils using signals transmitted by the tranmitter coil of the stylus | Dec 12, 1995 | Issued |
Array
(
[id] => 3878233
[patent_doc_number] => 05793982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Validating an installation plan containing multiple transports and redirectors by adding data structure of the modules to the plan if the indicated transport and redirector modules are unavailable'
[patent_app_type] => 1
[patent_app_number] => 8/570179
[patent_app_country] => US
[patent_app_date] => 1995-12-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/793/05793982.pdf
[firstpage_image] =>[orig_patent_app_number] => 570179
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/570179 | Validating an installation plan containing multiple transports and redirectors by adding data structure of the modules to the plan if the indicated transport and redirector modules are unavailable | Dec 6, 1995 | Issued |
Array
(
[id] => 3797454
[patent_doc_number] => 05758188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal'
[patent_app_type] => 1
[patent_app_number] => 8/555977
[patent_app_country] => US
[patent_app_date] => 1995-11-21
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[pdf_file] => patents/05/758/05758188.pdf
[firstpage_image] =>[orig_patent_app_number] => 555977
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/555977 | Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal | Nov 20, 1995 | Issued |
Array
(
[id] => 3804197
[patent_doc_number] => 05737633
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Serial data receiving device having a memory for storing a reception permit signal which enable or disable the device from hand-shaking with the transmitting device'
[patent_app_type] => 1
[patent_app_number] => 8/550325
[patent_app_country] => US
[patent_app_date] => 1995-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] => patents/05/737/05737633.pdf
[firstpage_image] =>[orig_patent_app_number] => 550325
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/550325 | Serial data receiving device having a memory for storing a reception permit signal which enable or disable the device from hand-shaking with the transmitting device | Oct 29, 1995 | Issued |
Array
(
[id] => 3920052
[patent_doc_number] => 05752082
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'System for multiplexing pins of a PC card socket and PC card bus adapter for providing audio communication between PC card and computer sound system'
[patent_app_type] => 1
[patent_app_number] => 8/544054
[patent_app_country] => US
[patent_app_date] => 1995-10-17
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[pdf_file] => patents/05/752/05752082.pdf
[firstpage_image] =>[orig_patent_app_number] => 544054
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/544054 | System for multiplexing pins of a PC card socket and PC card bus adapter for providing audio communication between PC card and computer sound system | Oct 16, 1995 | Issued |
Array
(
[id] => 3756316
[patent_doc_number] => 05787307
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Apparatus for draining off electric charges from a bus connector pins having a switch controller for controlling two switches where the second switch connects the pins to ground'
[patent_app_type] => 1
[patent_app_number] => 8/542369
[patent_app_country] => US
[patent_app_date] => 1995-10-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/787/05787307.pdf
[firstpage_image] =>[orig_patent_app_number] => 542369
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542369 | Apparatus for draining off electric charges from a bus connector pins having a switch controller for controlling two switches where the second switch connects the pins to ground | Oct 11, 1995 | Issued |
Array
(
[id] => 3837415
[patent_doc_number] => 05790892
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Information handling system for modifying coherency response set to allow intervention of a read command so that the intervention is not allowed by the system memory'
[patent_app_type] => 1
[patent_app_number] => 8/536885
[patent_app_country] => US
[patent_app_date] => 1995-09-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/790/05790892.pdf
[firstpage_image] =>[orig_patent_app_number] => 536885
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/536885 | Information handling system for modifying coherency response set to allow intervention of a read command so that the intervention is not allowed by the system memory | Sep 28, 1995 | Issued |
Array
(
[id] => 3797513
[patent_doc_number] => 05758191
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Method for buffer management in a disk drive having a first segment for storing burst data and a second segment used for write and read commands'
[patent_app_type] => 1
[patent_app_number] => 8/529528
[patent_app_country] => US
[patent_app_date] => 1995-09-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/758/05758191.pdf
[firstpage_image] =>[orig_patent_app_number] => 529528
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/529528 | Method for buffer management in a disk drive having a first segment for storing burst data and a second segment used for write and read commands | Sep 17, 1995 | Issued |