Melvyn J Andrews

Array ( [id] => 4049178 [patent_doc_number] => 05909055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Chip package device mountable on a mother board in whichever of facedown and wire bonding manners' [patent_app_type] => 1 [patent_app_number] => 9/084349 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 5213 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909055.pdf [firstpage_image] =>[orig_patent_app_number] => 084349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3990057 [patent_doc_number] => 05959353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/066859 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3173 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959353.pdf [firstpage_image] =>[orig_patent_app_number] => 066859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057489 [patent_doc_number] => 05932924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Leadframe having continuously reducing width and semiconductor device including such a leadframe' [patent_app_type] => 1 [patent_app_number] => 9/016988 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2075 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/932/05932924.pdf [firstpage_image] =>[orig_patent_app_number] => 016988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3927139 [patent_doc_number] => 05914535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Flip chip-on-flip chip multi-chip module' [patent_app_type] => 1 [patent_app_number] => 9/008457 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2033 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/914/05914535.pdf [firstpage_image] =>[orig_patent_app_number] => 008457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4048927 [patent_doc_number] => 05909037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Bi-level injection molded leadframe' [patent_app_type] => 1 [patent_app_number] => 9/005908 [patent_app_country] => US [patent_app_date] => 1998-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 620 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909037.pdf [firstpage_image] =>[orig_patent_app_number] => 005908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4038566 [patent_doc_number] => 05994784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Die positioning in integrated circuit packaging' [patent_app_type] => 1 [patent_app_number] => 8/993237 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1487 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994784.pdf [firstpage_image] =>[orig_patent_app_number] => 993237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3999371 [patent_doc_number] => 05920118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Chip-size package semiconductor' [patent_app_type] => 1 [patent_app_number] => 8/992259 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2141 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920118.pdf [firstpage_image] =>[orig_patent_app_number] => 992259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3940708 [patent_doc_number] => 05929519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor module including switching device chips and diode chips' [patent_app_type] => 1 [patent_app_number] => 8/979778 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 8400 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929519.pdf [firstpage_image] =>[orig_patent_app_number] => 979778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3987701 [patent_doc_number] => 05861661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Composite bump tape automated bonded structure' [patent_app_type] => 1 [patent_app_number] => 8/974454 [patent_app_country] => US [patent_app_date] => 1997-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 4552 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/861/05861661.pdf [firstpage_image] =>[orig_patent_app_number] => 974454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4080568 [patent_doc_number] => 05965940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Intermetal dielectric planarization by metal features layout modification' [patent_app_type] => 1 [patent_app_number] => 8/971869 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4171 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/965/05965940.pdf [firstpage_image] =>[orig_patent_app_number] => 971869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3766988 [patent_doc_number] => 05844311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Multichip module with heat sink and attachment means' [patent_app_type] => 1 [patent_app_number] => 8/972034 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3354 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844311.pdf [firstpage_image] =>[orig_patent_app_number] => 972034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4067985 [patent_doc_number] => 05895969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Thin type semiconductor device, module structure using the device and method of mounting the device on board' [patent_app_type] => 1 [patent_app_number] => 8/960332 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6205 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895969.pdf [firstpage_image] =>[orig_patent_app_number] => 960332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3788425 [patent_doc_number] => 05821590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Semiconductor interconnection device with both n- and p-doped regions' [patent_app_type] => 1 [patent_app_number] => 8/953645 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2590 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821590.pdf [firstpage_image] =>[orig_patent_app_number] => 953645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3746091 [patent_doc_number] => 05786628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging' [patent_app_type] => 1 [patent_app_number] => 8/951663 [patent_app_country] => US [patent_app_date] => 1997-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 39 [patent_no_of_words] => 12371 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786628.pdf [firstpage_image] =>[orig_patent_app_number] => 951663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4070227 [patent_doc_number] => 05866949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Chip scale ball grid array for integrated circuit packaging' [patent_app_type] => 1 [patent_app_number] => 8/947042 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7897 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866949.pdf [firstpage_image] =>[orig_patent_app_number] => 947042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057474 [patent_doc_number] => 05932923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Semiconductor device packages having dummy block leads and tie bars with extended portions to prevent formation of air traps in the encapsulate' [patent_app_type] => 1 [patent_app_number] => 8/943129 [patent_app_country] => US [patent_app_date] => 1997-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3008 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/932/05932923.pdf [firstpage_image] =>[orig_patent_app_number] => 943129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3954393 [patent_doc_number] => 05977635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Multi-level conductive structure including low capacitance material' [patent_app_type] => 1 [patent_app_number] => 8/939208 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4201 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977635.pdf [firstpage_image] =>[orig_patent_app_number] => 939208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892517 [patent_doc_number] => 05777367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Integrated structure active clamp for the protection of power devices against overvoltages' [patent_app_type] => 1 [patent_app_number] => 8/927304 [patent_app_country] => US [patent_app_date] => 1997-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3165 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777367.pdf [firstpage_image] =>[orig_patent_app_number] => 927304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3939266 [patent_doc_number] => 05939784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Shielded surface acoustical wave package' [patent_app_type] => 1 [patent_app_number] => 8/925915 [patent_app_country] => US [patent_app_date] => 1997-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3202 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939784.pdf [firstpage_image] =>[orig_patent_app_number] => 925915 [rel_patent_id] =>[rel_patent_doc_number] =>)