Search

Andrew L Sniezek

Examiner (ID: 13182)

Most Active Art Unit
2688
Art Unit(s)
2687, 2512, 2303, 2513, 2753, 2688, 2651, 2627, 2693, 2686
Total Applications
3202
Issued Applications
2564
Pending Applications
116
Abandoned Applications
504

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12595677 [patent_doc_number] => 20180090389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => INTEGRATED CIRCUIT COMPRISING MOS TRANSISTORS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/458109 [patent_app_country] => US [patent_app_date] => 2017-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15458109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/458109
INTEGRATED CIRCUIT COMPRISING MOS TRANSISTORS AND METHOD OF MANUFACTURING THE SAME Mar 13, 2017 Abandoned
Array ( [id] => 11971004 [patent_doc_number] => 20170275158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'INTEGRATION OF AIN ULTRASONIC TRANSDUCER ON A CMOS SUBSTRATE USING FUSION BONDING PROCESS' [patent_app_type] => utility [patent_app_number] => 15/457832 [patent_app_country] => US [patent_app_date] => 2017-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15457832 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/457832
Integration of AIN ultrasonic transducer on a CMOS substrate using fusion bonding process Mar 12, 2017 Issued
Array ( [id] => 11694523 [patent_doc_number] => 20170170240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SOLID-STATE IMAGE PICKUP DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/443663 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443663 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443663
Solid-state image pickup device and electronic apparatus Feb 26, 2017 Issued
Array ( [id] => 13392787 [patent_doc_number] => 20180247936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => FIELD EFFECT TRANSISTORS WITH REDUCED PARASITIC RESISTANCES AND METHOD [patent_app_type] => utility [patent_app_number] => 15/443381 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443381 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443381
Field effect transistors with reduced parasitic resistances and method Feb 26, 2017 Issued
Array ( [id] => 12457725 [patent_doc_number] => 09985114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Fin field effect transistor structure and method to form defect free merged source and drain epitaxy for low external resistance [patent_app_type] => utility [patent_app_number] => 15/435974 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8102 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15435974 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/435974
Fin field effect transistor structure and method to form defect free merged source and drain epitaxy for low external resistance Feb 16, 2017 Issued
Array ( [id] => 11630792 [patent_doc_number] => 20170140981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/417390 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/417390
Copper interconnect structure with manganese oxide barrier layer Jan 26, 2017 Issued
Array ( [id] => 11517460 [patent_doc_number] => 20170084534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'ELECTRICALLY CONDUCTIVE INTERCONNECT INCLUDING VIA HAVING INCREASED CONTACT SURFACE AREA' [patent_app_type] => utility [patent_app_number] => 15/364634 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364634 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364634
Electrically conductive interconnect including via having increased contact surface area Nov 29, 2016 Issued
Array ( [id] => 12147578 [patent_doc_number] => 09881835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-30 [patent_title] => 'Nanowire devices, systems, and methods of production' [patent_app_type] => utility [patent_app_number] => 15/331554 [patent_app_country] => US [patent_app_date] => 2016-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 6869 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15331554 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/331554
Nanowire devices, systems, and methods of production Oct 20, 2016 Issued
Array ( [id] => 12202566 [patent_doc_number] => 09905638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Silicon epitaxy for high aspect ratio, substantially perpendicular deep silicon trench' [patent_app_type] => utility [patent_app_number] => 15/281865 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 31 [patent_no_of_words] => 6280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281865 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281865
Silicon epitaxy for high aspect ratio, substantially perpendicular deep silicon trench Sep 29, 2016 Issued
Array ( [id] => 11532587 [patent_doc_number] => 20170092565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'Micro Heat Transfer Arrays, Micro Cold Plates, and Thermal Management Systems for Cooling Semiconductor Devices, and Methods for Using and Making Such Arrays, Plates, and Systems' [patent_app_type] => utility [patent_app_number] => 15/283013 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 31261 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283013 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/283013
Micro heat transfer arrays, micro cold plates, and thermal management systems for cooling semiconductor devices, and methods for using and making such arrays, plates, and systems Sep 29, 2016 Issued
Array ( [id] => 11517604 [patent_doc_number] => 20170084678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/264735 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9779 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264735 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/264735
Semiconductor device with terminals and manufacturing method of semiconductor device with terminals Sep 13, 2016 Issued
Array ( [id] => 12477927 [patent_doc_number] => 09991230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Integrated circuits and methods for fabricating integrated circuits and electrical interconnects for III-V semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/233235 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4667 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233235 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233235
Integrated circuits and methods for fabricating integrated circuits and electrical interconnects for III-V semiconductor devices Aug 9, 2016 Issued
Array ( [id] => 11459915 [patent_doc_number] => 20170053821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'WAFER PROCESSING BONDING ARRANGEMENT, WAFER LAMINATE, AND THIN WAFER MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/232175 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 11912 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232175 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/232175
Wafer processing bonding arrangement, wafer laminate, and thin wafer manufacturing method Aug 8, 2016 Issued
Array ( [id] => 12334740 [patent_doc_number] => 09947581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Method of forming a copper based interconnect structure [patent_app_type] => utility [patent_app_number] => 15/214760 [patent_app_country] => US [patent_app_date] => 2016-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4298 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15214760 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/214760
Method of forming a copper based interconnect structure Jul 19, 2016 Issued
Array ( [id] => 12310011 [patent_doc_number] => 09939710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => High-temperature isotropic plasma etching process to prevent electrical shorts [patent_app_type] => utility [patent_app_number] => 15/191569 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5933 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/191569
High-temperature isotropic plasma etching process to prevent electrical shorts Jun 23, 2016 Issued
Array ( [id] => 11315578 [patent_doc_number] => 20160351688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'METHOD OF MANUFACTURING INSULATED GATE SWITCHING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/157967 [patent_app_country] => US [patent_app_date] => 2016-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7576 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15157967 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/157967
METHOD OF MANUFACTURING INSULATED GATE SWITCHING DEVICE May 17, 2016 Abandoned
Array ( [id] => 13056441 [patent_doc_number] => 10049616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Display device and method for repairing the same [patent_app_type] => utility [patent_app_number] => 15/158444 [patent_app_country] => US [patent_app_date] => 2016-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10919 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15158444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/158444
Display device and method for repairing the same May 17, 2016 Issued
Array ( [id] => 12109258 [patent_doc_number] => 09865746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/071723 [patent_app_country] => US [patent_app_date] => 2016-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 69 [patent_no_of_words] => 34252 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15071723 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/071723
Semiconductor device Mar 15, 2016 Issued
Array ( [id] => 10993292 [patent_doc_number] => 20160190238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'NON-PLANAR SEMICONDUCTOR DEVICE WITH ASPECT RATIO TRAPPING' [patent_app_type] => utility [patent_app_number] => 15/066103 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2527 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066103 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/066103
Non-planar semiconductor device with aspect ratio trapping Mar 9, 2016 Issued
Array ( [id] => 10815487 [patent_doc_number] => 20160161647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'METHOD FOR PRODUCING MOLD FOR MINUTE PATTERN TRANSFER, METHOD FOR PRODUCING DIFFRACTION GRATING USING THE SAME, AND METHOD FOR PRODUCING ORGANIC EL ELEMENT INCLUDING THE DIFFRACTION GRATING' [patent_app_type] => utility [patent_app_number] => 15/041764 [patent_app_country] => US [patent_app_date] => 2016-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 39732 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15041764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/041764
METHOD FOR PRODUCING MOLD FOR MINUTE PATTERN TRANSFER, METHOD FOR PRODUCING DIFFRACTION GRATING USING THE SAME, AND METHOD FOR PRODUCING ORGANIC EL ELEMENT INCLUDING THE DIFFRACTION GRATING Feb 10, 2016 Abandoned
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