Search

Melody Noel Brown

Examiner (ID: 13321, Phone: (571)272-2599 , Office: P/2917 )

Most Active Art Unit
2917
Art Unit(s)
2915, 2901, 2917, 2911
Total Applications
11867
Issued Applications
11761
Pending Applications
2
Abandoned Applications
102

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19864763 [patent_doc_number] => 20250103549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => DATA PROCESSING METHOD AND APPARATUS, PROCESSOR, ELECTRONIC DEVICE AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/896789 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18896789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/896789
Improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor Sep 24, 2024 Issued
Array ( [id] => 19482195 [patent_doc_number] => 20240330237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/743637 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743637
Context load mechanism in a coarse-grained reconfigurable array processor Jun 13, 2024 Issued
Array ( [id] => 19481948 [patent_doc_number] => 20240329990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => Processing of Synchronization Barrier Instructions [patent_app_type] => utility [patent_app_number] => 18/740430 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740430
Processing of Synchronization Barrier Instructions Jun 10, 2024 Pending
Array ( [id] => 19383187 [patent_doc_number] => 20240273057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => Auto-Discovery Module for the Discovery of Reconfigurable Processors in a Pool of Heterogeneous Reconfigurable Processors [patent_app_type] => utility [patent_app_number] => 18/635114 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635114 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635114
Auto-Discovery Module for the Discovery of Reconfigurable Processors in a Pool of Heterogeneous Reconfigurable Processors Apr 14, 2024 Pending
Array ( [id] => 20290020 [patent_doc_number] => 20250315263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => Trace Cache Access Prediction and Read Enable [patent_app_type] => utility [patent_app_number] => 18/627035 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/627035
Trace Cache Access Prediction and Read Enable Apr 3, 2024 Pending
Array ( [id] => 19911858 [patent_doc_number] => 12288069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Stream data unit with multiple head registers [patent_app_type] => utility [patent_app_number] => 18/607703 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 17572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607703 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607703
Stream data unit with multiple head registers Mar 17, 2024 Issued
Array ( [id] => 19660532 [patent_doc_number] => 20240427597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => CONDITIONAL BRANCH INSTRUCTIONS FOR AGGREGATING CONDITIONAL BRANCH OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/604043 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604043
CONDITIONAL BRANCH INSTRUCTIONS FOR AGGREGATING CONDITIONAL BRANCH OPERATIONS Mar 12, 2024 Pending
Array ( [id] => 19499202 [patent_doc_number] => 20240338220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => APPARATUS AND METHOD FOR IMPLEMENTING MANY DIFFERENT LOOP TYPES IN A MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 18/603171 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603171 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603171
APPARATUS AND METHOD FOR IMPLEMENTING MANY DIFFERENT LOOP TYPES IN A MICROPROCESSOR Mar 11, 2024 Pending
Array ( [id] => 19588284 [patent_doc_number] => 20240385841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => FETCHING BEYOND PREDICTED-TAKEN BRANCH INSTRUCTIONS IN FETCH BUNDLES OF PROCESSOR-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 18/594899 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594899 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594899
FETCHING BEYOND PREDICTED-TAKEN BRANCH INSTRUCTIONS IN FETCH BUNDLES OF PROCESSOR-BASED DEVICES Mar 3, 2024 Pending
Array ( [id] => 20195388 [patent_doc_number] => 20250272098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => CONTROLLING SPECULATIVE ACTIONS BASED ON A HIT/MISS PREDICTOR [patent_app_type] => utility [patent_app_number] => 18/585283 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18585283 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/585283
CONTROLLING SPECULATIVE ACTIONS BASED ON A HIT/MISS PREDICTOR Feb 22, 2024 Issued
Array ( [id] => 19383188 [patent_doc_number] => 20240273058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => Domain Adaptive Processor For Wireless Communication [patent_app_type] => utility [patent_app_number] => 18/439936 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439936 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439936
Domain Adaptive Processor For Wireless Communication Feb 12, 2024 Pending
Array ( [id] => 19558475 [patent_doc_number] => 20240370267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => RUNTIME CONFIGURABLE MODULAR PROCESSING TILE [patent_app_type] => utility [patent_app_number] => 18/430952 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430952
RUNTIME CONFIGURABLE MODULAR PROCESSING TILE Feb 1, 2024 Pending
Array ( [id] => 20130903 [patent_doc_number] => 12373216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Conditional branch instructions [patent_app_type] => utility [patent_app_number] => 18/427411 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427411 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/427411
Conditional branch instructions Jan 29, 2024 Issued
Array ( [id] => 20137970 [patent_doc_number] => 20250245014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => SYSTEM AND METHOD FOR DISTRIBUTED FORWARDING LOGIC FOR CYCLIC DATA-PIPELINE COHERENCY [patent_app_type] => utility [patent_app_number] => 18/424989 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424989 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424989
SYSTEM AND METHOD FOR DISTRIBUTED FORWARDING LOGIC FOR CYCLIC DATA-PIPELINE COHERENCY Jan 28, 2024 Pending
Array ( [id] => 19235760 [patent_doc_number] => 20240192955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => LOOP EXECUTION IN A RECONFIGURABLE COMPUTE FABRIC USING FLOW CONTROLLERS FOR RESPECTIVE SYNCHRONOUS FLOWS [patent_app_type] => utility [patent_app_number] => 18/426237 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426237 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426237
LOOP EXECUTION IN A RECONFIGURABLE COMPUTE FABRIC USING FLOW CONTROLLERS FOR RESPECTIVE SYNCHRONOUS FLOWS Jan 28, 2024 Pending
Array ( [id] => 19334291 [patent_doc_number] => 20240248721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => OPERATION DISTRIBUTION ACROSS MULTIPLE PROCESSING CORES [patent_app_type] => utility [patent_app_number] => 18/414230 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414230 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414230
OPERATION DISTRIBUTION ACROSS MULTIPLE PROCESSING CORES Jan 15, 2024 Pending
Array ( [id] => 19267556 [patent_doc_number] => 20240211259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => PREFETCHING WITH SATURATION CONTROL [patent_app_type] => utility [patent_app_number] => 18/396792 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396792 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/396792
PREFETCHING WITH SATURATION CONTROL Dec 26, 2023 Pending
Array ( [id] => 19099665 [patent_doc_number] => 20240118893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => PULSE MODULATION CONTROL SYSTEM, DEVICE, AND METHOD [patent_app_type] => utility [patent_app_number] => 18/544453 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544453 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544453
Multi-channel pulse modulation control system, device, and method based on RISC-V custom instructions Dec 18, 2023 Issued
Array ( [id] => 19334293 [patent_doc_number] => 20240248723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => PROCESSOR AND METHOD OF CONTROLLING PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/536760 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536760
PROCESSOR AND METHOD OF CONTROLLING PROCESSOR Dec 11, 2023 Pending
Array ( [id] => 19175253 [patent_doc_number] => 20240161227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/532245 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 52745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18532245 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/532245
Architecture for block sparse operations on a systolic array Dec 6, 2023 Issued
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