Search

Tan V Mai

Examiner (ID: 13419, Phone: (571)272-3726 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2183, 2121, 2182, 2193, 2301, 2306, 2124, 2786, 2302
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19917576 [patent_doc_number] => 12292946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-06 [patent_title] => Method for implementing formal verification of optimized multiplier via SCA-SAT synergy [patent_app_type] => utility [patent_app_number] => 18/967676 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1590 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 799 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967676 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/967676
Method for implementing formal verification of optimized multiplier via SCA-SAT synergy Dec 3, 2024 Issued
Array ( [id] => 19794978 [patent_doc_number] => 12235927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-02-25 [patent_title] => Process-in-memory architecture based on resistive random access memory and matrix decomposition acceleration algorithm [patent_app_type] => utility [patent_app_number] => 18/922350 [patent_app_country] => US [patent_app_date] => 2024-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4184 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18922350 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/922350
Process-in-memory architecture based on resistive random access memory and matrix decomposition acceleration algorithm Oct 20, 2024 Issued
Array ( [id] => 19719069 [patent_doc_number] => 12204606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-21 [patent_title] => Restructuring matrix processing on a computing device [patent_app_type] => utility [patent_app_number] => 18/793225 [patent_app_country] => US [patent_app_date] => 2024-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 22553 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18793225 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/793225
Restructuring matrix processing on a computing device Aug 1, 2024 Issued
Array ( [id] => 19596050 [patent_doc_number] => 12153898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-11-26 [patent_title] => Method and system for weight memory mapping for streaming operation of giant generative artifical intelligence hardware [patent_app_type] => utility [patent_app_number] => 18/744211 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7648 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744211 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744211
Method and system for weight memory mapping for streaming operation of giant generative artifical intelligence hardware Jun 13, 2024 Issued
Array ( [id] => 19485262 [patent_doc_number] => 20240333304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MATRIX COMPRESSION ACCELERATOR SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 18/738203 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738203
MATRIX COMPRESSION ACCELERATOR SYSTEM AND METHOD Jun 9, 2024 Pending
Array ( [id] => 19917793 [patent_doc_number] => 12293163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-06 [patent_title] => Split accumulator with a shared adder [patent_app_type] => utility [patent_app_number] => 18/679915 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 7386 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679915 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679915
Split accumulator with a shared adder May 30, 2024 Issued
Array ( [id] => 19405903 [patent_doc_number] => 20240289414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM [patent_app_type] => utility [patent_app_number] => 18/650280 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650280 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650280
Information processing apparatus, information processing method, and information processing program Apr 29, 2024 Issued
Array ( [id] => 19514638 [patent_doc_number] => 20240346324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => METHODS AND SYSTEMS FOR ENHANCED SENSOR ASSESSMENTS FOR PREDICTING SECONDARY ENDPOINTS [patent_app_type] => utility [patent_app_number] => 18/637783 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637783 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637783
Methods and systems for enhanced sensor assessments for predicting secondary endpoints Apr 16, 2024 Issued
Array ( [id] => 19558734 [patent_doc_number] => 20240370526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => PERFORMING MATRIX MULTIPLICATION IN HARDWARE [patent_app_type] => utility [patent_app_number] => 18/638285 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18638285 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/638285
PERFORMING MATRIX MULTIPLICATION IN HARDWARE Apr 16, 2024 Pending
Array ( [id] => 19383498 [patent_doc_number] => 20240273368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => Vector Computation Unit in a Neural Network Processor [patent_app_type] => utility [patent_app_number] => 18/636640 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636640
Vector computation unit in a neural network processor Apr 15, 2024 Issued
Array ( [id] => 19243820 [patent_doc_number] => 12014266 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-18 [patent_title] => Systems and methods for optimized data storage and analysis based on cognitive emulation [patent_app_type] => utility [patent_app_number] => 18/598567 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598567
Systems and methods for optimized data storage and analysis based on cognitive emulation Mar 6, 2024 Issued
Array ( [id] => 19267694 [patent_doc_number] => 20240211397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => Processor Cluster Address Generation [patent_app_type] => utility [patent_app_number] => 18/438932 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438932
Processor cluster address generation Feb 11, 2024 Issued
Array ( [id] => 19267833 [patent_doc_number] => 20240211537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => Methods and Apparatus for Performing Video Processing Matrix Operations Within a Memory Array [patent_app_type] => utility [patent_app_number] => 18/433974 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433974
Methods and Apparatus for Performing Video Processing Matrix Operations Within a Memory Array Feb 5, 2024 Pending
Array ( [id] => 19204946 [patent_doc_number] => 20240176845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => METHOD AND DEVICE FOR MATRIX MULTIPLICATION OPTIMIZATION USING VECTOR REGISTERS [patent_app_type] => utility [patent_app_number] => 18/434068 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434068
METHOD AND DEVICE FOR MATRIX MULTIPLICATION OPTIMIZATION USING VECTOR REGISTERS Feb 5, 2024 Pending
Array ( [id] => 19276348 [patent_doc_number] => 12026478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-02 [patent_title] => Multiply accumulate (MAC) unit with split accumulator [patent_app_type] => utility [patent_app_number] => 18/408309 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 12389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408309 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408309
Multiply accumulate (MAC) unit with split accumulator Jan 8, 2024 Issued
Array ( [id] => 19129291 [patent_doc_number] => 20240134644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MULTIPLY [patent_app_type] => utility [patent_app_number] => 18/400961 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400961
SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MULTIPLY Dec 28, 2023 Pending
Array ( [id] => 19280898 [patent_doc_number] => 20240217372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => BILEVEL COORDINATED OPTIMIZATION METHOD FOR FIXED AND MOBILE CHARGING FACILITIES ON HIGHWAYS [patent_app_type] => utility [patent_app_number] => 18/391662 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/391662
Bilevel coordinated optimization method for fixed and mobile charging facilities on highways Dec 20, 2023 Issued
Array ( [id] => 19872934 [patent_doc_number] => 12265797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Apparatus and method for processing floating-point numbers [patent_app_type] => utility [patent_app_number] => 18/544313 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 13271 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544313
Apparatus and method for processing floating-point numbers Dec 17, 2023 Issued
Array ( [id] => 19236184 [patent_doc_number] => 20240193379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => HYBRID ANALOG-DIGITAL MATRIX PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/538172 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538172
Hybrid analog-digital matrix processors Dec 12, 2023 Issued
Array ( [id] => 19443393 [patent_doc_number] => 12093663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-17 [patent_title] => System and methods for constructing single-stage [patent_app_type] => utility [patent_app_number] => 18/532546 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 6924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18532546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/532546
System and methods for constructing single-stage Dec 6, 2023 Issued
Menu