![](/images/general/no_picture/200_user.png)
Matthew O Savage
Examiner (ID: 1392, Phone: (571)272-1146 , Office: P/1773 )
Most Active Art Unit | 1306 |
Art Unit(s) | 1778, 1724, 1306, 1723, 1797, 1773, 1776 |
Total Applications | 2718 |
Issued Applications | 1844 |
Pending Applications | 157 |
Abandoned Applications | 717 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3764975
[patent_doc_number] => 05721707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Erase voltage control circuit for an electrically erasable non-volatile memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/787907
[patent_app_country] => US
[patent_app_date] => 1997-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 4550
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721707.pdf
[firstpage_image] =>[orig_patent_app_number] => 787907
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/787907 | Erase voltage control circuit for an electrically erasable non-volatile memory cell | Jan 22, 1997 | Issued |
Array
(
[id] => 3742015
[patent_doc_number] => 05694364
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Semiconductor integrated circuit device having a test mode for reliability evaluation'
[patent_app_type] => 1
[patent_app_number] => 8/779186
[patent_app_country] => US
[patent_app_date] => 1997-01-06
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[pdf_file] => patents/05/694/05694364.pdf
[firstpage_image] =>[orig_patent_app_number] => 779186
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/779186 | Semiconductor integrated circuit device having a test mode for reliability evaluation | Jan 5, 1997 | Issued |
Array
(
[id] => 3836140
[patent_doc_number] => 05732027
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Memory having selectable output strength'
[patent_app_type] => 1
[patent_app_number] => 8/777488
[patent_app_country] => US
[patent_app_date] => 1996-12-30
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[pdf_file] => patents/05/732/05732027.pdf
[firstpage_image] =>[orig_patent_app_number] => 777488
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777488 | Memory having selectable output strength | Dec 29, 1996 | Issued |
Array
(
[id] => 3867640
[patent_doc_number] => 05706231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Semiconductor memory device having a redundant memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/768088
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/706/05706231.pdf
[firstpage_image] =>[orig_patent_app_number] => 768088
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768088 | Semiconductor memory device having a redundant memory cell | Dec 15, 1996 | Issued |
Array
(
[id] => 3756712
[patent_doc_number] => 05717632
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Apparatus and method for multiple-level storage in non-volatile memories'
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[patent_app_country] => US
[patent_app_date] => 1996-11-27
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[pdf_file] => patents/05/717/05717632.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757988 | Apparatus and method for multiple-level storage in non-volatile memories | Nov 26, 1996 | Issued |
Array
(
[id] => 3733207
[patent_doc_number] => 05673233
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-30
[patent_title] => 'Synchronous memory allowing early read command in write to read transitions'
[patent_app_type] => 1
[patent_app_number] => 8/746410
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[firstpage_image] =>[orig_patent_app_number] => 746410
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/746410 | Synchronous memory allowing early read command in write to read transitions | Nov 7, 1996 | Issued |
Array
(
[id] => 3808079
[patent_doc_number] => 05781499
[patent_country] => US
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[patent_issue_date] => 1998-07-14
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/741285
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[pdf_file] => patents/05/781/05781499.pdf
[firstpage_image] =>[orig_patent_app_number] => 741285
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741285 | Semiconductor memory device | Oct 29, 1996 | Issued |
Array
(
[id] => 3747554
[patent_doc_number] => 05699314
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Video random access memory device and method implementing independent two we nibble control'
[patent_app_type] => 1
[patent_app_number] => 8/732943
[patent_app_country] => US
[patent_app_date] => 1996-10-17
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[pdf_file] => patents/05/699/05699314.pdf
[firstpage_image] =>[orig_patent_app_number] => 732943
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/732943 | Video random access memory device and method implementing independent two we nibble control | Oct 16, 1996 | Issued |
Array
(
[id] => 3851900
[patent_doc_number] => 05708607
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Data read circuit of a memory'
[patent_app_type] => 1
[patent_app_number] => 8/724886
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[firstpage_image] =>[orig_patent_app_number] => 724886
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/724886 | Data read circuit of a memory | Oct 2, 1996 | Issued |
Array
(
[id] => 3741861
[patent_doc_number] => 05694353
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Non-volatile ferroelectric memory device equipped with reference voltage generator for exactly regulating reference voltage to the mid point between two logic level and method of reading out data bit therefrom'
[patent_app_type] => 1
[patent_app_number] => 8/718828
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[firstpage_image] =>[orig_patent_app_number] => 718828
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/718828 | Non-volatile ferroelectric memory device equipped with reference voltage generator for exactly regulating reference voltage to the mid point between two logic level and method of reading out data bit therefrom | Sep 23, 1996 | Issued |
Array
(
[id] => 3697381
[patent_doc_number] => 05696731
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[patent_issue_date] => 1997-12-09
[patent_title] => 'Semiconductor memory device using internal voltage obtained by boosting supply voltage'
[patent_app_type] => 1
[patent_app_number] => 8/708951
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[firstpage_image] =>[orig_patent_app_number] => 708951
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/708951 | Semiconductor memory device using internal voltage obtained by boosting supply voltage | Sep 5, 1996 | Issued |
Array
(
[id] => 3852056
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[patent_issue_date] => 1998-01-13
[patent_title] => 'Semiconductor memory device with reduced current consumption during precharge and reading periods'
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Array
(
[id] => 3736564
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[patent_title] => 'Semiconductor memory device including divisional decoder circuit composed of NMOS transistors'
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Array
(
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Array
(
[id] => 3657857
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/686385 | Word driver circuit and a memory circuit using the same | Jul 24, 1996 | Issued |
Array
(
[id] => 3697906
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Array
(
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Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/654886 | Method of rewriting data in a microprocessor additionally provided with a flash memory | May 28, 1996 | Issued |