Search

Matthew O Savage

Examiner (ID: 1392, Phone: (571)272-1146 , Office: P/1773 )

Most Active Art Unit
1306
Art Unit(s)
1778, 1724, 1306, 1723, 1797, 1773, 1776
Total Applications
2718
Issued Applications
1844
Pending Applications
157
Abandoned Applications
717

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3764975 [patent_doc_number] => 05721707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Erase voltage control circuit for an electrically erasable non-volatile memory cell' [patent_app_type] => 1 [patent_app_number] => 8/787907 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4550 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721707.pdf [firstpage_image] =>[orig_patent_app_number] => 787907 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/787907
Erase voltage control circuit for an electrically erasable non-volatile memory cell Jan 22, 1997 Issued
Array ( [id] => 3742015 [patent_doc_number] => 05694364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Semiconductor integrated circuit device having a test mode for reliability evaluation' [patent_app_type] => 1 [patent_app_number] => 8/779186 [patent_app_country] => US [patent_app_date] => 1997-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 13555 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694364.pdf [firstpage_image] =>[orig_patent_app_number] => 779186 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779186
Semiconductor integrated circuit device having a test mode for reliability evaluation Jan 5, 1997 Issued
Array ( [id] => 3836140 [patent_doc_number] => 05732027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Memory having selectable output strength' [patent_app_type] => 1 [patent_app_number] => 8/777488 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7227 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732027.pdf [firstpage_image] =>[orig_patent_app_number] => 777488 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777488
Memory having selectable output strength Dec 29, 1996 Issued
Array ( [id] => 3867640 [patent_doc_number] => 05706231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Semiconductor memory device having a redundant memory cell' [patent_app_type] => 1 [patent_app_number] => 8/768088 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 10686 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706231.pdf [firstpage_image] =>[orig_patent_app_number] => 768088 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768088
Semiconductor memory device having a redundant memory cell Dec 15, 1996 Issued
Array ( [id] => 3756712 [patent_doc_number] => 05717632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Apparatus and method for multiple-level storage in non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 8/757988 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 9193 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717632.pdf [firstpage_image] =>[orig_patent_app_number] => 757988 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757988
Apparatus and method for multiple-level storage in non-volatile memories Nov 26, 1996 Issued
Array ( [id] => 3733207 [patent_doc_number] => 05673233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Synchronous memory allowing early read command in write to read transitions' [patent_app_type] => 1 [patent_app_number] => 8/746410 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7046 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673233.pdf [firstpage_image] =>[orig_patent_app_number] => 746410 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746410
Synchronous memory allowing early read command in write to read transitions Nov 7, 1996 Issued
Array ( [id] => 3808079 [patent_doc_number] => 05781499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/741285 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 58 [patent_no_of_words] => 5158 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781499.pdf [firstpage_image] =>[orig_patent_app_number] => 741285 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/741285
Semiconductor memory device Oct 29, 1996 Issued
Array ( [id] => 3747554 [patent_doc_number] => 05699314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Video random access memory device and method implementing independent two we nibble control' [patent_app_type] => 1 [patent_app_number] => 8/732943 [patent_app_country] => US [patent_app_date] => 1996-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3128 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699314.pdf [firstpage_image] =>[orig_patent_app_number] => 732943 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/732943
Video random access memory device and method implementing independent two we nibble control Oct 16, 1996 Issued
Array ( [id] => 3851900 [patent_doc_number] => 05708607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Data read circuit of a memory' [patent_app_type] => 1 [patent_app_number] => 8/724886 [patent_app_country] => US [patent_app_date] => 1996-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4245 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708607.pdf [firstpage_image] =>[orig_patent_app_number] => 724886 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724886
Data read circuit of a memory Oct 2, 1996 Issued
Array ( [id] => 3741861 [patent_doc_number] => 05694353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Non-volatile ferroelectric memory device equipped with reference voltage generator for exactly regulating reference voltage to the mid point between two logic level and method of reading out data bit therefrom' [patent_app_type] => 1 [patent_app_number] => 8/718828 [patent_app_country] => US [patent_app_date] => 1996-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13689 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694353.pdf [firstpage_image] =>[orig_patent_app_number] => 718828 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/718828
Non-volatile ferroelectric memory device equipped with reference voltage generator for exactly regulating reference voltage to the mid point between two logic level and method of reading out data bit therefrom Sep 23, 1996 Issued
Array ( [id] => 3697381 [patent_doc_number] => 05696731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Semiconductor memory device using internal voltage obtained by boosting supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/708951 [patent_app_country] => US [patent_app_date] => 1996-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3918 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696731.pdf [firstpage_image] =>[orig_patent_app_number] => 708951 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708951
Semiconductor memory device using internal voltage obtained by boosting supply voltage Sep 5, 1996 Issued
Array ( [id] => 3852056 [patent_doc_number] => 05708615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Semiconductor memory device with reduced current consumption during precharge and reading periods' [patent_app_type] => 1 [patent_app_number] => 8/708733 [patent_app_country] => US [patent_app_date] => 1996-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5300 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708615.pdf [firstpage_image] =>[orig_patent_app_number] => 708733 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708733
Semiconductor memory device with reduced current consumption during precharge and reading periods Sep 4, 1996 Issued
Array ( [id] => 3736564 [patent_doc_number] => 05652731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Semiconductor memory device including divisional decoder circuit composed of NMOS transistors' [patent_app_type] => 1 [patent_app_number] => 8/691591 [patent_app_country] => US [patent_app_date] => 1996-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4892 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652731.pdf [firstpage_image] =>[orig_patent_app_number] => 691591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691591
Semiconductor memory device including divisional decoder circuit composed of NMOS transistors Aug 1, 1996 Issued
Array ( [id] => 3851786 [patent_doc_number] => 05708599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Semiconductor memory device capable of reducing power consumption' [patent_app_type] => 1 [patent_app_number] => 8/691151 [patent_app_country] => US [patent_app_date] => 1996-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 3936 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708599.pdf [firstpage_image] =>[orig_patent_app_number] => 691151 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691151
Semiconductor memory device capable of reducing power consumption Jul 31, 1996 Issued
Array ( [id] => 3657857 [patent_doc_number] => 05640359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Word driver circuit and a memory circuit using the same' [patent_app_type] => 1 [patent_app_number] => 8/686385 [patent_app_country] => US [patent_app_date] => 1996-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4430 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640359.pdf [firstpage_image] =>[orig_patent_app_number] => 686385 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/686385
Word driver circuit and a memory circuit using the same Jul 24, 1996 Issued
Array ( [id] => 3697906 [patent_doc_number] => 05691935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Memory element and method of operation thereof' [patent_app_type] => 1 [patent_app_number] => 8/675388 [patent_app_country] => US [patent_app_date] => 1996-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 15600 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691935.pdf [firstpage_image] =>[orig_patent_app_number] => 675388 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/675388
Memory element and method of operation thereof Jul 1, 1996 Issued
Array ( [id] => 3659182 [patent_doc_number] => 05684745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'SRAM device with a bit line discharge circuit for low power' [patent_app_type] => 1 [patent_app_number] => 8/673487 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1869 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684745.pdf [firstpage_image] =>[orig_patent_app_number] => 673487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673487
SRAM device with a bit line discharge circuit for low power Jun 30, 1996 Issued
Array ( [id] => 3740892 [patent_doc_number] => 05666308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Writing circuit for non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 8/668785 [patent_app_country] => US [patent_app_date] => 1996-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1282 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666308.pdf [firstpage_image] =>[orig_patent_app_number] => 668785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668785
Writing circuit for non-volatile memory Jun 23, 1996 Issued
Array ( [id] => 3732058 [patent_doc_number] => 05682353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Self adjusting sense amplifier clock delay circuit' [patent_app_type] => 1 [patent_app_number] => 8/665151 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5865 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682353.pdf [firstpage_image] =>[orig_patent_app_number] => 665151 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665151
Self adjusting sense amplifier clock delay circuit Jun 12, 1996 Issued
Array ( [id] => 3747289 [patent_doc_number] => 05699297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Method of rewriting data in a microprocessor additionally provided with a flash memory' [patent_app_type] => 1 [patent_app_number] => 8/654886 [patent_app_country] => US [patent_app_date] => 1996-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2771 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699297.pdf [firstpage_image] =>[orig_patent_app_number] => 654886 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/654886
Method of rewriting data in a microprocessor additionally provided with a flash memory May 28, 1996 Issued
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