Search

Jeffrey P Zimmerman

Examiner (ID: 1394)

Most Active Art Unit
3623
Art Unit(s)
3624, 3628, 3684, 3623
Total Applications
201
Issued Applications
21
Pending Applications
4
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3836900 [patent_doc_number] => 05760607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'System comprising field programmable gate array and intelligent memory' [patent_app_type] => 1 [patent_app_number] => 8/888607 [patent_app_country] => US [patent_app_date] => 1997-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 6277 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760607.pdf [firstpage_image] =>[orig_patent_app_number] => 888607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888607
System comprising field programmable gate array and intelligent memory Jul 6, 1997 Issued
Array ( [id] => 3853907 [patent_doc_number] => 05719507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Logic gate having transmission gate for electrically configurable device multiplexer' [patent_app_type] => 1 [patent_app_number] => 8/803686 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3353 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719507.pdf [firstpage_image] =>[orig_patent_app_number] => 803686 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803686
Logic gate having transmission gate for electrically configurable device multiplexer Feb 23, 1997 Issued
Array ( [id] => 3847473 [patent_doc_number] => 05744978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Variable load device responsive to a circuit parameter' [patent_app_type] => 1 [patent_app_number] => 8/783573 [patent_app_country] => US [patent_app_date] => 1997-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2817 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744978.pdf [firstpage_image] =>[orig_patent_app_number] => 783573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783573
Variable load device responsive to a circuit parameter Jan 14, 1997 Issued
Array ( [id] => 3752305 [patent_doc_number] => 05717342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Output buffer incorporating shared intermediate nodes' [patent_app_type] => 1 [patent_app_number] => 8/745410 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5000 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717342.pdf [firstpage_image] =>[orig_patent_app_number] => 745410 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/745410
Output buffer incorporating shared intermediate nodes Nov 21, 1996 Issued
Array ( [id] => 3799082 [patent_doc_number] => 05726586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Programmable application specific integrated circuit and logic cell therefor' [patent_app_type] => 1 [patent_app_number] => 8/744225 [patent_app_country] => US [patent_app_date] => 1996-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6731 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726586.pdf [firstpage_image] =>[orig_patent_app_number] => 744225 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/744225
Programmable application specific integrated circuit and logic cell therefor Nov 4, 1996 Issued
Array ( [id] => 3746896 [patent_doc_number] => 05754062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Current switching logic type circuit with small current consumption' [patent_app_type] => 1 [patent_app_number] => 8/735834 [patent_app_country] => US [patent_app_date] => 1996-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 19449 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 726 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754062.pdf [firstpage_image] =>[orig_patent_app_number] => 735834 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735834
Current switching logic type circuit with small current consumption Oct 22, 1996 Issued
Array ( [id] => 3766972 [patent_doc_number] => 05742178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Programmable voltage stabilizing circuit for a programmable integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/740118 [patent_app_country] => US [patent_app_date] => 1996-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1517 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742178.pdf [firstpage_image] =>[orig_patent_app_number] => 740118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/740118
Programmable voltage stabilizing circuit for a programmable integrated circuit device Oct 21, 1996 Issued
Array ( [id] => 3893138 [patent_doc_number] => 05714890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Programmable logic device with fixed and programmable memory' [patent_app_type] => 1 [patent_app_number] => 8/789095 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1909 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/714/05714890.pdf [firstpage_image] =>[orig_patent_app_number] => 789095 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789095
Programmable logic device with fixed and programmable memory Oct 10, 1996 Issued
Array ( [id] => 3884776 [patent_doc_number] => 05748009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Programmable logic cell' [patent_app_type] => 1 [patent_app_number] => 8/707840 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 10490 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748009.pdf [firstpage_image] =>[orig_patent_app_number] => 707840 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707840
Programmable logic cell Sep 8, 1996 Issued
Array ( [id] => 3746880 [patent_doc_number] => 05754061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Bi-CMOS circuits with enhanced power supply noise suppression and enhanced speed' [patent_app_type] => 1 [patent_app_number] => 8/718015 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 94 [patent_no_of_words] => 15980 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754061.pdf [firstpage_image] =>[orig_patent_app_number] => 718015 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/718015
Bi-CMOS circuits with enhanced power supply noise suppression and enhanced speed Sep 2, 1996 Issued
Array ( [id] => 3799097 [patent_doc_number] => 05726587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'BiCMOS tri-state buffer with low leakage current' [patent_app_type] => 1 [patent_app_number] => 8/711315 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2577 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726587.pdf [firstpage_image] =>[orig_patent_app_number] => 711315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711315
BiCMOS tri-state buffer with low leakage current Sep 2, 1996 Issued
Array ( [id] => 3831616 [patent_doc_number] => 05731713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'TTL to CMOS level translator with voltage and threshold compensation' [patent_app_type] => 1 [patent_app_number] => 8/704179 [patent_app_country] => US [patent_app_date] => 1996-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 8671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731713.pdf [firstpage_image] =>[orig_patent_app_number] => 704179 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/704179
TTL to CMOS level translator with voltage and threshold compensation Aug 26, 1996 Issued
Array ( [id] => 3742634 [patent_doc_number] => 05698996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Data processing with self-timed feature and low power transition detection' [patent_app_type] => 1 [patent_app_number] => 8/692795 [patent_app_country] => US [patent_app_date] => 1996-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1490 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698996.pdf [firstpage_image] =>[orig_patent_app_number] => 692795 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/692795
Data processing with self-timed feature and low power transition detection Jul 31, 1996 Issued
Array ( [id] => 3734350 [patent_doc_number] => 05703497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Current source responsive to supply voltage variations' [patent_app_type] => 1 [patent_app_number] => 8/686007 [patent_app_country] => US [patent_app_date] => 1996-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2904 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703497.pdf [firstpage_image] =>[orig_patent_app_number] => 686007 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/686007
Current source responsive to supply voltage variations Jul 24, 1996 Issued
Array ( [id] => 3831645 [patent_doc_number] => 05731715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Glitch-free clock enable circuit' [patent_app_type] => 1 [patent_app_number] => 8/679574 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3648 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731715.pdf [firstpage_image] =>[orig_patent_app_number] => 679574 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679574
Glitch-free clock enable circuit Jul 14, 1996 Issued
Array ( [id] => 3729505 [patent_doc_number] => 05672984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Programmable logic array having power-saving banks' [patent_app_type] => 1 [patent_app_number] => 8/654938 [patent_app_country] => US [patent_app_date] => 1996-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4475 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/672/05672984.pdf [firstpage_image] =>[orig_patent_app_number] => 654938 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/654938
Programmable logic array having power-saving banks May 28, 1996 Issued
Array ( [id] => 3746838 [patent_doc_number] => 05754058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Output buffer controlling circuit of a multibit integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/653564 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1903 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754058.pdf [firstpage_image] =>[orig_patent_app_number] => 653564 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653564
Output buffer controlling circuit of a multibit integrated circuit May 23, 1996 Issued
Array ( [id] => 3777760 [patent_doc_number] => 05773996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Multiple-valued logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/650251 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 62 [patent_no_of_words] => 9025 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773996.pdf [firstpage_image] =>[orig_patent_app_number] => 650251 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/650251
Multiple-valued logic circuit May 21, 1996 Issued
Array ( [id] => 3905768 [patent_doc_number] => 05751169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Emitter coupled logic (ECL) gate which generates intermediate signals of four different voltages' [patent_app_type] => 1 [patent_app_number] => 8/641865 [patent_app_country] => US [patent_app_date] => 1996-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2186 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751169.pdf [firstpage_image] =>[orig_patent_app_number] => 641865 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641865
Emitter coupled logic (ECL) gate which generates intermediate signals of four different voltages May 1, 1996 Issued
Array ( [id] => 3776747 [patent_doc_number] => 05850150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Final stage clock buffer in a clock distribution network' [patent_app_type] => 1 [patent_app_number] => 8/640660 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6458 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850150.pdf [firstpage_image] =>[orig_patent_app_number] => 640660 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/640660
Final stage clock buffer in a clock distribution network Apr 30, 1996 Issued
Menu