Search

Paul J Killos

Examiner (ID: 14937)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1204, 1206
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10950702 [patent_doc_number] => 20140353723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'High Voltage Durability III-Nitride Device' [patent_app_type] => utility [patent_app_number] => 14/459726 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3032 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459726 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459726
High voltage durability III-nitride device Aug 13, 2014 Issued
Array ( [id] => 10115536 [patent_doc_number] => 09150408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Method of etching a wafer' [patent_app_type] => utility [patent_app_number] => 14/338754 [patent_app_country] => US [patent_app_date] => 2014-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3318 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14338754 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/338754
Method of etching a wafer Jul 22, 2014 Issued
Array ( [id] => 10631616 [patent_doc_number] => 09349772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM' [patent_app_type] => utility [patent_app_number] => 14/261543 [patent_app_country] => US [patent_app_date] => 2014-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 6656 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14261543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/261543
Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM Apr 24, 2014 Issued
Array ( [id] => 10426161 [patent_doc_number] => 20150311173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'STRUCTURES AND METHODS FOR REDUCING CORROSION IN WIRE BONDS' [patent_app_type] => utility [patent_app_number] => 14/262381 [patent_app_country] => US [patent_app_date] => 2014-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14262381 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/262381
Structures for reducing corrosion in wire bonds Apr 24, 2014 Issued
Array ( [id] => 10426332 [patent_doc_number] => 20150311343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'CHANNEL REGION DOPANT CONTROL IN FIN FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/260953 [patent_app_country] => US [patent_app_date] => 2014-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14260953 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/260953
Method of forming channel region dopant control in fin field effect transistor Apr 23, 2014 Issued
Array ( [id] => 10426110 [patent_doc_number] => 20150311121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'SELECTIVELY GROWN SELF-ALIGNED FINS FOR DEEP ISOLATION INTEGRATION' [patent_app_type] => utility [patent_app_number] => 14/260724 [patent_app_country] => US [patent_app_date] => 2014-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14260724 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/260724
Selectively grown self-aligned fins for deep isolation integration Apr 23, 2014 Issued
Array ( [id] => 10245585 [patent_doc_number] => 20150130580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'COMMON MODE FILTER AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/259536 [patent_app_country] => US [patent_app_date] => 2014-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3767 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14259536 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/259536
COMMON MODE FILTER AND MANUFACTURING METHOD THEREOF Apr 22, 2014 Abandoned
Array ( [id] => 9642632 [patent_doc_number] => 20140220743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/252780 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7031 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14252780 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/252780
POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME Apr 14, 2014 Abandoned
Array ( [id] => 9329324 [patent_doc_number] => 20140056106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'SOUND SOURCE SIGNAL FILTERING APPARATUS BASED ON CALCULATED DISTANCE BETWEEN MICROPHONE AND SOUND SOURCE' [patent_app_type] => utility [patent_app_number] => 14/065900 [patent_app_country] => US [patent_app_date] => 2013-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7262 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14065900 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/065900
Sound source signal filtering apparatus based on calculated distance between microphone and sound source Oct 28, 2013 Issued
Array ( [id] => 9327905 [patent_doc_number] => 20140054687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE' [patent_app_type] => utility [patent_app_number] => 14/057465 [patent_app_country] => US [patent_app_date] => 2013-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14057465 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/057465
MOSFET device with reduced breakdown voltage Oct 17, 2013 Issued
Array ( [id] => 9568111 [patent_doc_number] => 20140185824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'FORMING VIRTUAL MICROPHONE ARRAYS USING DUAL OMNIDIRECTIONAL MICROPHONE ARRAY (DOMA)' [patent_app_type] => utility [patent_app_number] => 13/959707 [patent_app_country] => US [patent_app_date] => 2013-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 18993 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13959707 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/959707
FORMING VIRTUAL MICROPHONE ARRAYS USING DUAL OMNIDIRECTIONAL MICROPHONE ARRAY (DOMA) Aug 4, 2013 Abandoned
Array ( [id] => 10537820 [patent_doc_number] => 09263455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines' [patent_app_type] => utility [patent_app_number] => 13/948746 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 32 [patent_no_of_words] => 6853 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13948746 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/948746
Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines Jul 22, 2013 Issued
Array ( [id] => 9809669 [patent_doc_number] => 20150021614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'CONTROLLED ON AND OFF TIME SCHEME FOR MONOLITHIC CASCODED POWER TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 13/946415 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13946415 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/946415
Controlled on and off time scheme for monolithic cascoded power transistors Jul 18, 2013 Issued
Array ( [id] => 10570351 [patent_doc_number] => 09293529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Semiconductor device with an array of lamellas and a micro-electro-mechanical resonator' [patent_app_type] => utility [patent_app_number] => 13/945113 [patent_app_country] => US [patent_app_date] => 2013-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7500 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13945113 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/945113
Semiconductor device with an array of lamellas and a micro-electro-mechanical resonator Jul 17, 2013 Issued
Array ( [id] => 10590605 [patent_doc_number] => 09312225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Bump structure for stacked dies' [patent_app_type] => utility [patent_app_number] => 13/943543 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5056 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943543 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943543
Bump structure for stacked dies Jul 15, 2013 Issued
Array ( [id] => 10971817 [patent_doc_number] => 20140374852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'Electrical Shielding in a MEMS Leadframe Package' [patent_app_type] => utility [patent_app_number] => 13/926726 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13926726 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/926726
Electrical shielding in a MEMS leadframe package Jun 24, 2013 Issued
Array ( [id] => 10971767 [patent_doc_number] => 20140374802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'BIPOLAR TRANSISTOR WITH MASKLESS SELF-ALIGNED EMITTER' [patent_app_type] => utility [patent_app_number] => 13/926644 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3451 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13926644 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/926644
Method of forming a bipolar transistor with maskless self-aligned emitter Jun 24, 2013 Issued
Array ( [id] => 10971813 [patent_doc_number] => 20140374848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'SEMICONDUCTOR SENSOR DEVICE WITH METAL LID' [patent_app_type] => utility [patent_app_number] => 13/924628 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924628 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/924628
SEMICONDUCTOR SENSOR DEVICE WITH METAL LID Jun 23, 2013 Abandoned
Array ( [id] => 10590601 [patent_doc_number] => 09312221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Variable capacitance devices' [patent_app_type] => utility [patent_app_number] => 13/916620 [patent_app_country] => US [patent_app_date] => 2013-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 8729 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13916620 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/916620
Variable capacitance devices Jun 12, 2013 Issued
Array ( [id] => 10950831 [patent_doc_number] => 20140353852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'METHOD FOR PROCESSING A CARRIER AND A CARRIER' [patent_app_type] => utility [patent_app_number] => 13/904122 [patent_app_country] => US [patent_app_date] => 2013-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11453 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13904122 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/904122
Method of processing a carrier with alignment marks May 28, 2013 Issued
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