Stephen F Husar

Array ( [id] => 11320764 [patent_doc_number] => 09519507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-13 [patent_title] => 'Executing an instruction of currently active thread before context switch upon receiving inactive context ID to be activated' [patent_app_type] => utility [patent_app_number] => 14/701871 [patent_app_country] => US [patent_app_date] => 2015-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3059 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14701871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11251966 [patent_doc_number] => 09477468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Character data string match determination by loading registers at most up to memory block boundary and comparing to avoid unwarranted exception' [patent_app_type] => utility [patent_app_number] => 14/560001 [patent_app_country] => US [patent_app_date] => 2014-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 23719 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14560001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9912098 [patent_doc_number] => 20150067301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'MICROPROCESSOR WITH BOOT INDICATOR THAT INDICATES A BOOT ISA OF THE MICROPROCESSOR AS EITHER THE X86 ISA OR THE ARM ISA' [patent_app_type] => utility [patent_app_number] => 14/526029 [patent_app_country] => US [patent_app_date] => 2014-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14526029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9866661 [patent_doc_number] => 20150046680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'DYNAMIC AND SELECTIVE CORE DISABLEMENT AND RECONFIGURATION IN A MULTI-CORE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/522931 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7005 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14522931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9900749 [patent_doc_number] => 20150055949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'NODE INTERCONNECT ARCHITECTURE TO IMPLEMENT HIGH-PERFORMANCE SUPERCOMPUTER' [patent_app_type] => utility [patent_app_number] => 14/510653 [patent_app_country] => US [patent_app_date] => 2014-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7396 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14510653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11238969 [patent_doc_number] => 09465614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Parallel execution of instructions in processing units and adjusting power mode based on monitored data dependency over a period of time' [patent_app_type] => utility [patent_app_number] => 14/195657 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6238 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14195657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11332942 [patent_doc_number] => 09524187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-20 [patent_title] => 'Executing instruction with threshold indicating nearing of completion of transaction' [patent_app_type] => utility [patent_app_number] => 14/194769 [patent_app_country] => US [patent_app_date] => 2014-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 17991 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14194769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9563762 [patent_doc_number] => 20140181475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'Parallel Processing of a Sequential Program Using Hardware Generated Threads and Their Instruction Groups Executing on Plural Execution Units and Accessing Register File Segments Using Dependency Inheritance Vectors Across Multiple Engines' [patent_app_type] => utility [patent_app_number] => 14/194589 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15040 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14194589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11299587 [patent_doc_number] => 09507595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Execution of multi-byte memory access instruction specifying endian mode that overrides current global endian mode' [patent_app_type] => utility [patent_app_number] => 14/193491 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8517 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14193491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10357209 [patent_doc_number] => 20150242214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'DYNAMIC PREDICTION OF HARDWARE TRANSACTION RESOURCE REQUIREMENTS' [patent_app_type] => utility [patent_app_number] => 14/191554 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 20046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14191554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10357212 [patent_doc_number] => 20150242218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'DEFERRAL INSTRUCTION FOR MANAGING TRANSACTIONAL ABORTS IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS' [patent_app_type] => utility [patent_app_number] => 14/191639 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14191639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10357210 [patent_doc_number] => 20150242215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'PREDICTING THE LENGTH OF A TRANSACTION' [patent_app_type] => utility [patent_app_number] => 14/191615 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 17270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14191615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10342369 [patent_doc_number] => 20150227374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'EARLY LOOP BUFFER ENTRY' [patent_app_type] => utility [patent_app_number] => 14/179204 [patent_app_country] => US [patent_app_date] => 2014-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11179593 [patent_doc_number] => 09411587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Method of prefetch optimizing by measuring execution time of instruction sequence cycling through each selectable hardware prefetch depth and cycling through disabling each software prefetch instruction' [patent_app_type] => utility [patent_app_number] => 14/102512 [patent_app_country] => US [patent_app_date] => 2013-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7866 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9386455 [patent_doc_number] => 20140089938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'MULTI-THREAD PROCESSOR AND ITS HARDWARE THREAD SCHEDULING METHOD' [patent_app_type] => utility [patent_app_number] => 14/092498 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6583 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14092498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11239001 [patent_doc_number] => 09465647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM' [patent_app_type] => utility [patent_app_number] => 14/048451 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5586 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14048451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9224959 [patent_doc_number] => 20140019734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'DATA PROCESSING APPARATUS AND METHOD USING CHECKPOINTING' [patent_app_type] => utility [patent_app_number] => 14/031281 [patent_app_country] => US [patent_app_date] => 2013-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4291 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14031281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9673182 [patent_doc_number] => 20140237045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK' [patent_app_type] => utility [patent_app_number] => 13/975943 [patent_app_country] => US [patent_app_date] => 2013-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8598 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13975943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11345191 [patent_doc_number] => 09529597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Multithread processor with different schedule pattern cycle state for handling interrupt processing' [patent_app_type] => utility [patent_app_number] => 13/964418 [patent_app_country] => US [patent_app_date] => 2013-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11259 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13964418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10637375 [patent_doc_number] => 09354878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Last branch record register for storing taken branch information and transactional memory transaction indicator to be used in transaction execution analysis' [patent_app_type] => utility [patent_app_number] => 13/918147 [patent_app_country] => US [patent_app_date] => 2013-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918147 [rel_patent_id] =>[rel_patent_doc_number] =>)