Search

Gail Poulos

Examiner (ID: 16133)

Most Active Art Unit
1804
Art Unit(s)
1806, 1802, 1804
Total Applications
113
Issued Applications
56
Pending Applications
0
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17559772 [patent_doc_number] => 11316501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-26 [patent_title] => Resampling technique for arbitrary sampling rate conversion [patent_app_type] => utility [patent_app_number] => 17/519833 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8660 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 749 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519833
Resampling technique for arbitrary sampling rate conversion Nov 4, 2021 Issued
Array ( [id] => 17530586 [patent_doc_number] => 11303295 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => SDM encoder and related signal processing system [patent_app_type] => utility [patent_app_number] => 17/452403 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 9699 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452403
SDM encoder and related signal processing system Oct 25, 2021 Issued
Array ( [id] => 18218631 [patent_doc_number] => 11593573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Chopper stabilized analog multiplier unit element with binary weighted charge transfer capacitors [patent_app_type] => utility [patent_app_number] => 17/334890 [patent_app_country] => US [patent_app_date] => 2021-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 8221 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334890
Chopper stabilized analog multiplier unit element with binary weighted charge transfer capacitors May 30, 2021 Issued
Array ( [id] => 17284556 [patent_doc_number] => 11201604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-14 [patent_title] => Resampling algorithm based on window function [patent_app_type] => utility [patent_app_number] => 17/215945 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8751 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 663 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215945
Resampling algorithm based on window function Mar 28, 2021 Issued
Array ( [id] => 17667044 [patent_doc_number] => 11360740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-14 [patent_title] => Single-stage hardware sorting blocks and associated multiway merge sorting networks [patent_app_type] => utility [patent_app_number] => 17/190843 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 47 [patent_no_of_words] => 14346 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190843 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190843
Single-stage hardware sorting blocks and associated multiway merge sorting networks Mar 2, 2021 Issued
Array ( [id] => 16964786 [patent_doc_number] => 20210216285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => RANDOM NUMBER GENERATION AND ACQUISITION METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/181978 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181978
Random number generation and acquisition method and device Feb 21, 2021 Issued
Array ( [id] => 17651366 [patent_doc_number] => 11354093 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-07 [patent_title] => Integer and characters prefix based methodologies combined with parallel data sort methodology enhance the execution performance of any string sorting algorithm [patent_app_type] => utility [patent_app_number] => 17/074122 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 79 [patent_no_of_words] => 15403 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 618 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074122
Integer and characters prefix based methodologies combined with parallel data sort methodology enhance the execution performance of any string sorting algorithm Oct 18, 2020 Issued
Array ( [id] => 18204309 [patent_doc_number] => 11586701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Low-power adder circuit [patent_app_type] => utility [patent_app_number] => 17/063813 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9559 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/063813
Low-power adder circuit Oct 5, 2020 Issued
Array ( [id] => 18072895 [patent_doc_number] => 11531729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Bitwise digital circuit and method for performing approximate operations [patent_app_type] => utility [patent_app_number] => 17/060994 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 9041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060994
Bitwise digital circuit and method for performing approximate operations Sep 30, 2020 Issued
Array ( [id] => 17744282 [patent_doc_number] => 11392349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Multiply-accumulate operation device [patent_app_type] => utility [patent_app_number] => 17/039002 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8645 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 595 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039002
Multiply-accumulate operation device Sep 29, 2020 Issued
Array ( [id] => 17651368 [patent_doc_number] => 11354095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Vehicular arithmetic operation processing device, server computer, and non-transitory storage medium [patent_app_type] => utility [patent_app_number] => 17/019521 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3300 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019521
Vehicular arithmetic operation processing device, server computer, and non-transitory storage medium Sep 13, 2020 Issued
Array ( [id] => 16514760 [patent_doc_number] => 20200394018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => MULTI-ADDEND ADDER CIRCUIT FOR STOCHASTIC COMPUTING [patent_app_type] => utility [patent_app_number] => 17/004893 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004893
Multi-addend adder circuit for stochastic computing Aug 26, 2020 Issued
Array ( [id] => 16508094 [patent_doc_number] => 20200387350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => DOT PRODUCT CALCULATORS AND METHODS OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/001455 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001455 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001455
Dot product calculators and methods of operating the same Aug 23, 2020 Issued
Array ( [id] => 17542706 [patent_doc_number] => 11307827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Tiled switch matrix data permutation circuit [patent_app_type] => utility [patent_app_number] => 16/928958 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6253 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928958
Tiled switch matrix data permutation circuit Jul 13, 2020 Issued
Array ( [id] => 17409215 [patent_doc_number] => 11250102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Optimizing linear programming models using different solvers [patent_app_type] => utility [patent_app_number] => 16/928849 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928849 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928849
Optimizing linear programming models using different solvers Jul 13, 2020 Issued
Array ( [id] => 17699368 [patent_doc_number] => 11373097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Optimized neural network input stride method and apparatus [patent_app_type] => utility [patent_app_number] => 16/929087 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6955 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929087 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929087
Optimized neural network input stride method and apparatus Jul 13, 2020 Issued
Array ( [id] => 16616044 [patent_doc_number] => 20210034697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => MATRIX PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/928242 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928242 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928242
Matrix processing apparatus Jul 13, 2020 Issued
Array ( [id] => 17252815 [patent_doc_number] => 11188304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => Validating microprocessor performance [patent_app_type] => utility [patent_app_number] => 16/917956 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917956 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917956
Validating microprocessor performance Jun 30, 2020 Issued
Array ( [id] => 16363140 [patent_doc_number] => 20200319891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => ARITHMETIC LOGIC UNIT [patent_app_type] => utility [patent_app_number] => 16/910608 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910608 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910608
ARITHMETIC LOGIC UNIT Jun 23, 2020 Abandoned
Array ( [id] => 16363103 [patent_doc_number] => 20200319854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => RANDOM NUMBER GENERATION AND ACQUISITION METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 16/906840 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906840
Random number generation and acquisition method and device Jun 18, 2020 Issued
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