Search

Matthew C Graham

Examiner (ID: 16287, Phone: (571)272-7116 , Office: P/3993 )

Most Active Art Unit
3103
Art Unit(s)
3683, 3613, 3103, 2202, 3104, 3993, 3303
Total Applications
2166
Issued Applications
1848
Pending Applications
68
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18790175 [patent_doc_number] => 20230378960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => PHASE LOCK LOOP (PLL) SYNCHRONIZATION [patent_app_type] => utility [patent_app_number] => 18/225477 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225477 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225477
PHASE LOCK LOOP (PLL) SYNCHRONIZATION Jul 23, 2023 Pending
Array ( [id] => 19460577 [patent_doc_number] => 12101095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Fractional divider with duty cycle regulation and low subharmonic content [patent_app_type] => utility [patent_app_number] => 18/317582 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317582 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317582
Fractional divider with duty cycle regulation and low subharmonic content May 14, 2023 Issued
Array ( [id] => 19357381 [patent_doc_number] => 12057846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Delay lock loop circuits and methods for operating same [patent_app_type] => utility [patent_app_number] => 18/301299 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301299 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301299
Delay lock loop circuits and methods for operating same Apr 16, 2023 Issued
Array ( [id] => 18899372 [patent_doc_number] => 20240014857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Wireless Power Transfer With In-Band Virtualized Wired Communications [patent_app_type] => utility [patent_app_number] => 18/298072 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/298072
Wireless power transfer with in-band virtualized wired communications Apr 9, 2023 Issued
Array ( [id] => 18797477 [patent_doc_number] => 11831322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Digitally calibrated programmable clock phase generation circuit [patent_app_type] => utility [patent_app_number] => 18/126889 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126889 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126889
Digitally calibrated programmable clock phase generation circuit Mar 26, 2023 Issued
Array ( [id] => 18975992 [patent_doc_number] => 20240056084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 18/189599 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189599 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/189599
Digital phase locked loop and methods of operating same Mar 23, 2023 Issued
Array ( [id] => 18834491 [patent_doc_number] => 20230403018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT, PHASE LOCKED LOOP (PLL) CIRCUIT, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/176339 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176339
Semiconductor integrated circuit, phase locked loop (PLL) circuit, and system Feb 27, 2023 Issued
Array ( [id] => 18790176 [patent_doc_number] => 20230378961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => METHODS AND APPARATUS TO RETIME DATA USING A PROGRAMMABLE DELAY [patent_app_type] => utility [patent_app_number] => 18/115682 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18115682 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/115682
Methods and apparatus to retime data using a programmable delay Feb 27, 2023 Issued
Array ( [id] => 18730135 [patent_doc_number] => 20230344433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => PERIOD ERROR CORRECTION IN DIGITAL FREQUENCY LOCKED LOOPS [patent_app_type] => utility [patent_app_number] => 18/114595 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/114595
Period error correction in digital frequency locked loops Feb 26, 2023 Issued
Array ( [id] => 18697217 [patent_doc_number] => 20230327676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => ULTRA-LOW POWER INSTANT LOCK PHASE LOCK LOOP (PLL) [patent_app_type] => utility [patent_app_number] => 18/113601 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113601 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113601
Ultra-low power instant lock phase lock loop (PLL) Feb 22, 2023 Issued
Array ( [id] => 19109190 [patent_doc_number] => 11962309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Phase adjusting circuit, delay locking circuit, and memory [patent_app_type] => utility [patent_app_number] => 18/169285 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9204 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169285 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169285
Phase adjusting circuit, delay locking circuit, and memory Feb 14, 2023 Issued
Array ( [id] => 18849769 [patent_doc_number] => 20230412173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => DELAY LOCKED LOOP CIRCUITRY AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/166169 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166169 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166169
Delay locked loop circuitry and memory device Feb 7, 2023 Issued
Array ( [id] => 19109193 [patent_doc_number] => 11962312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Frequency-locked and phase-locked loop-based clock glitch detection for security [patent_app_type] => utility [patent_app_number] => 18/106398 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8683 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18106398 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/106398
Frequency-locked and phase-locked loop-based clock glitch detection for security Feb 5, 2023 Issued
Array ( [id] => 18540928 [patent_doc_number] => 20230246039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/096045 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096045
Semiconductor device Jan 11, 2023 Issued
Array ( [id] => 18395240 [patent_doc_number] => 20230163461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MILLIMETER-WAVE SCALABLE PLL-COUPLED ARRAY FOR PHASED-ARRAY APPLICATIONS [patent_app_type] => utility [patent_app_number] => 18/151697 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151697 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151697
Millimeter-wave scalable PLL-coupled array for phased-array applications Jan 8, 2023 Issued
Array ( [id] => 18984210 [patent_doc_number] => 11909405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-20 [patent_title] => Digital coarse locking in digital phase-locked loops [patent_app_type] => utility [patent_app_number] => 18/151861 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151861
Digital coarse locking in digital phase-locked loops Jan 8, 2023 Issued
Array ( [id] => 18999696 [patent_doc_number] => 11916559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Delay-locked loop with widened lock range [patent_app_type] => utility [patent_app_number] => 18/090748 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7458 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090748 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090748
Delay-locked loop with widened lock range Dec 28, 2022 Issued
Array ( [id] => 18913527 [patent_doc_number] => 11876522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Duty-cycle corrector circuit [patent_app_type] => utility [patent_app_number] => 18/146287 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 9775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146287 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146287
Duty-cycle corrector circuit Dec 22, 2022 Issued
Array ( [id] => 18891669 [patent_doc_number] => 11870451 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-09 [patent_title] => Frequency synthesizer using voltage-controlled oscillator (VCO) core of wideband synthesizer with integrated VCO [patent_app_type] => utility [patent_app_number] => 18/084805 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084805 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/084805
Frequency synthesizer using voltage-controlled oscillator (VCO) core of wideband synthesizer with integrated VCO Dec 19, 2022 Issued
Array ( [id] => 18515285 [patent_doc_number] => 20230231567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => CALIBRATION OF A TIME-TO-DIGITAL CONVERTER USING A VIRTUAL PHASE-LOCKED LOOP [patent_app_type] => utility [patent_app_number] => 18/083396 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083396 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/083396
Calibration of a time-to-digital converter using a virtual phase-locked loop Dec 15, 2022 Issued
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