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Dennis S Loo

Examiner (ID: 16674)

Most Active Art Unit
2856
Art Unit(s)
2856
Total Applications
63
Issued Applications
58
Pending Applications
2
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5101387 [patent_doc_number] => 20070184649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics' [patent_app_type] => utility [patent_app_number] => 11/348428 [patent_app_country] => US [patent_app_date] => 2006-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2522 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184649.pdf [firstpage_image] =>[orig_patent_app_number] => 11348428 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348428
Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics Feb 5, 2006 Issued
Array ( [id] => 5656037 [patent_doc_number] => 20060141773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Method of forming metal line in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/321119 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20060141773.pdf [firstpage_image] =>[orig_patent_app_number] => 11321119 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321119
Method of forming metal line in semiconductor device Dec 27, 2005 Abandoned
Array ( [id] => 899878 [patent_doc_number] => 07338860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Methods of forming non-volatile memory device having floating gate' [patent_app_type] => utility [patent_app_number] => 11/268038 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6849 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/338/07338860.pdf [firstpage_image] =>[orig_patent_app_number] => 11268038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268038
Methods of forming non-volatile memory device having floating gate Nov 6, 2005 Issued
Array ( [id] => 5193985 [patent_doc_number] => 20070082469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Forming heaters for phase change memories' [patent_app_type] => utility [patent_app_number] => 11/248488 [patent_app_country] => US [patent_app_date] => 2005-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20070082469.pdf [firstpage_image] =>[orig_patent_app_number] => 11248488 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/248488
Forming heaters for phase change memories Oct 11, 2005 Abandoned
Array ( [id] => 5637599 [patent_doc_number] => 20060068572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/225898 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3536 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20060068572.pdf [firstpage_image] =>[orig_patent_app_number] => 11225898 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225898
Semiconductor device manufacturing method Sep 13, 2005 Issued
Array ( [id] => 864727 [patent_doc_number] => 07368379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Multi-layer interconnect structure for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/197009 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/368/07368379.pdf [firstpage_image] =>[orig_patent_app_number] => 11197009 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197009
Multi-layer interconnect structure for semiconductor devices Aug 3, 2005 Issued
Array ( [id] => 5765091 [patent_doc_number] => 20060018175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Electrical via connection and associated contact means as well as a method for their manufacture' [patent_app_type] => utility [patent_app_number] => 11/185808 [patent_app_country] => US [patent_app_date] => 2005-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5257 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20060018175.pdf [firstpage_image] =>[orig_patent_app_number] => 11185808 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/185808
Electrical via connection and associated contact means as well as a method for their manufacture Jul 20, 2005 Abandoned
Array ( [id] => 5865675 [patent_doc_number] => 20060099806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method of forming electrode for compound semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/183908 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1745 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20060099806.pdf [firstpage_image] =>[orig_patent_app_number] => 11183908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183908
Method of forming electrode for compound semiconductor device Jul 18, 2005 Abandoned
Array ( [id] => 5242410 [patent_doc_number] => 20070020905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Low resistance contact in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/184074 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3911 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020905.pdf [firstpage_image] =>[orig_patent_app_number] => 11184074 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/184074
Low resistance contact in a semiconductor device Jul 18, 2005 Issued
Array ( [id] => 5073097 [patent_doc_number] => 20070013072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'METHOD AND STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF' [patent_app_type] => utility [patent_app_number] => 11/160468 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4458 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20070013072.pdf [firstpage_image] =>[orig_patent_app_number] => 11160468 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160468
Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof Jun 23, 2005 Issued
Array ( [id] => 5625516 [patent_doc_number] => 20060264021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Offset solder bump method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/131828 [patent_app_country] => US [patent_app_date] => 2005-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20060264021.pdf [firstpage_image] =>[orig_patent_app_number] => 11131828 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131828
Offset solder bump method and apparatus May 16, 2005 Abandoned
Array ( [id] => 7056109 [patent_doc_number] => 20050277284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/118369 [patent_app_country] => US [patent_app_date] => 2005-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20050277284.pdf [firstpage_image] =>[orig_patent_app_number] => 11118369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/118369
Method for manufacturing a semiconductor device May 1, 2005 Abandoned
Array ( [id] => 7197285 [patent_doc_number] => 20050164486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Semiconductor substrates including I/O redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same' [patent_app_type] => utility [patent_app_number] => 11/083518 [patent_app_country] => US [patent_app_date] => 2005-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4889 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20050164486.pdf [firstpage_image] =>[orig_patent_app_number] => 11083518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/083518
Semiconductor substrates including I/O redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same Mar 17, 2005 Issued
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