Quocan B Vo
Examiner (ID: 17405)
Most Active Art Unit | 1798 |
Art Unit(s) | 1798 |
Total Applications | 81 |
Issued Applications | 47 |
Pending Applications | 2 |
Abandoned Applications | 32 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 18111449
[patent_doc_number] => 20230004329
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => MANAGED FETCHING AND EXECUTION OF COMMANDS FROM SUBMISSION QUEUES
[patent_app_type] => utility
[patent_app_number] => 17/940598
[patent_app_country] => US
[patent_app_date] => 2022-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16724
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940598
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/940598 | MANAGED FETCHING AND EXECUTION OF COMMANDS FROM SUBMISSION QUEUES | Sep 7, 2022 | Pending |
Array
(
[id] => 18207802
[patent_doc_number] => 20230054059
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-23
[patent_title] => Gateway Fabric Ports
[patent_app_type] => utility
[patent_app_number] => 17/823237
[patent_app_country] => US
[patent_app_date] => 2022-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22477
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823237
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/823237 | Gateway Fabric Ports | Aug 29, 2022 | Pending |
Array
(
[id] => 18079366
[patent_doc_number] => 20220404978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => SPECULATIVE HINT-TRIGGERED ACTIVATION OF PAGES IN MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/895357
[patent_app_country] => US
[patent_app_date] => 2022-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7146
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895357
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/895357 | SPECULATIVE HINT-TRIGGERED ACTIVATION OF PAGES IN MEMORY | Aug 24, 2022 | Pending |
Array
(
[id] => 18038456
[patent_doc_number] => 20220382672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => PAGING IN THIN-PROVISIONED DISAGGREGATED MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/818816
[patent_app_country] => US
[patent_app_date] => 2022-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9719
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818816
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/818816 | PAGING IN THIN-PROVISIONED DISAGGREGATED MEMORY | Aug 9, 2022 | Pending |
Array
(
[id] => 18918032
[patent_doc_number] => 11880311
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-23
[patent_title] => Methods for controlling asynchronous FIFO memory and data transmission system utilizing the same
[patent_app_type] => utility
[patent_app_number] => 17/881634
[patent_app_country] => US
[patent_app_date] => 2022-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6597
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881634
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/881634 | Methods for controlling asynchronous FIFO memory and data transmission system utilizing the same | Aug 4, 2022 | Issued |
Array
(
[id] => 18454068
[patent_doc_number] => 20230195348
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => METHOD OF ORGANIZING A PROGRAMMABLE ATOMIC UNIT INSTRUCTION MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/870254
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12036
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870254
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/870254 | METHOD OF ORGANIZING A PROGRAMMABLE ATOMIC UNIT INSTRUCTION MEMORY | Jul 20, 2022 | Pending |
Array
(
[id] => 17984446
[patent_doc_number] => 20220350483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => METHOD AND APPARATUS TO ENABLE INDIVIDUAL NON VOLATILE MEMORY EXPRESS (NVME) INPUT/OUTPUT (IO) QUEUES ON DIFFERING NETWORK ADDRESSES OF AN NVME CONTROLLER
[patent_app_type] => utility
[patent_app_number] => 17/862145
[patent_app_country] => US
[patent_app_date] => 2022-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8002
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862145
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/862145 | METHOD AND APPARATUS TO ENABLE INDIVIDUAL NON VOLATILE MEMORY EXPRESS (NVME) INPUT/OUTPUT (IO) QUEUES ON DIFFERING NETWORK ADDRESSES OF AN NVME CONTROLLER | Jul 10, 2022 | Pending |
Array
(
[id] => 17899345
[patent_doc_number] => 20220309007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => Data Write Method, Apparatus, and System
[patent_app_type] => utility
[patent_app_number] => 17/806659
[patent_app_country] => US
[patent_app_date] => 2022-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7945
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806659
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/806659 | Data Write Method, Apparatus, and System | Jun 12, 2022 | Pending |
Array
(
[id] => 18727997
[patent_doc_number] => 20230342290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => DIE-AWARE SCHEDULER
[patent_app_type] => utility
[patent_app_number] => 17/726391
[patent_app_country] => US
[patent_app_date] => 2022-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 42674
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726391
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/726391 | DIE-AWARE SCHEDULER | Apr 20, 2022 | Pending |
Array
(
[id] => 18659965
[patent_doc_number] => 20230305972
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => MEMORY TUNNELING INTERFACE
[patent_app_type] => utility
[patent_app_number] => 17/704553
[patent_app_country] => US
[patent_app_date] => 2022-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6119
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704553
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/704553 | MEMORY TUNNELING INTERFACE | Mar 24, 2022 | Pending |
Array
(
[id] => 17706942
[patent_doc_number] => 20220206948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => DYNAMIC BANKING AND BIT SEPARATION IN MEMORIES
[patent_app_type] => utility
[patent_app_number] => 17/699401
[patent_app_country] => US
[patent_app_date] => 2022-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10592
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699401
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/699401 | DYNAMIC BANKING AND BIT SEPARATION IN MEMORIES | Mar 20, 2022 | Pending |
Array
(
[id] => 17690211
[patent_doc_number] => 20220197504
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => MEMORY DEVICES AND SYSTEMS FOR HOST CONTROLLED ENABLEMENT OF AUTOMATIC BACKGROUND OPERATIONS IN A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/692241
[patent_app_country] => US
[patent_app_date] => 2022-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3728
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692241
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/692241 | MEMORY DEVICES AND SYSTEMS FOR HOST CONTROLLED ENABLEMENT OF AUTOMATIC BACKGROUND OPERATIONS IN A MEMORY DEVICE | Mar 10, 2022 | Pending |
Array
(
[id] => 18584817
[patent_doc_number] => 20230267081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => PERIPHERAL COMPONENT HANDLING OF MEMORY READ REQUESTS
[patent_app_type] => utility
[patent_app_number] => 17/678174
[patent_app_country] => US
[patent_app_date] => 2022-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10284
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678174
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/678174 | PERIPHERAL COMPONENT HANDLING OF MEMORY READ REQUESTS | Feb 22, 2022 | Pending |
Array
(
[id] => 17613687
[patent_doc_number] => 20220155967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => Congestion Mitigation in A Multi-Tiered Distributed Storage System
[patent_app_type] => utility
[patent_app_number] => 17/667630
[patent_app_country] => US
[patent_app_date] => 2022-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8180
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667630
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/667630 | Congestion Mitigation in A Multi-Tiered Distributed Storage System | Feb 8, 2022 | Pending |
Array
(
[id] => 17613732
[patent_doc_number] => 20220156012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => SELECTING A WRITE OPERATION MODE FROM MULTIPLE WRITE OPERATION MODES
[patent_app_type] => utility
[patent_app_number] => 17/589451
[patent_app_country] => US
[patent_app_date] => 2022-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11552
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589451
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/589451 | SELECTING A WRITE OPERATION MODE FROM MULTIPLE WRITE OPERATION MODES | Jan 30, 2022 | Pending |
Array
(
[id] => 18703358
[patent_doc_number] => 11789869
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-17
[patent_title] => Contention tracking for latency reduction of exclusive operations
[patent_app_type] => utility
[patent_app_number] => 17/580360
[patent_app_country] => US
[patent_app_date] => 2022-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 12506
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580360
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/580360 | Contention tracking for latency reduction of exclusive operations | Jan 19, 2022 | Issued |
Array
(
[id] => 17597684
[patent_doc_number] => 20220147258
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-12
[patent_title] => SYSTEMS AND METHODS FOR BALANCING MULTIPLE PARTITIONS OF NON-VOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/648540
[patent_app_country] => US
[patent_app_date] => 2022-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5849
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648540
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648540 | SYSTEMS AND METHODS FOR BALANCING MULTIPLE PARTITIONS OF NON-VOLATILE MEMORY | Jan 19, 2022 | Pending |
Array
(
[id] => 17915740
[patent_doc_number] => 20220318136
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => I/O Agent
[patent_app_type] => utility
[patent_app_number] => 17/648071
[patent_app_country] => US
[patent_app_date] => 2022-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12165
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648071
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648071 | I/O agent | Jan 13, 2022 | Issued |
Array
(
[id] => 18486908
[patent_doc_number] => 20230214254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => PCIe TLP Size And Alignment Management
[patent_app_type] => utility
[patent_app_number] => 17/569362
[patent_app_country] => US
[patent_app_date] => 2022-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5551
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569362
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/569362 | PCIe TLP Size And Alignment Management | Jan 4, 2022 | Pending |
Array
(
[id] => 17551335
[patent_doc_number] => 20220122677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => Programming A Memory Device
[patent_app_type] => utility
[patent_app_number] => 17/566080
[patent_app_country] => US
[patent_app_date] => 2021-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8183
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566080
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/566080 | Programming a memory device | Dec 29, 2021 | Issued |