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Vi N Tran
Examiner (ID: 177)
Most Active Art Unit | 2117 |
Art Unit(s) | 2117 |
Total Applications | 96 |
Issued Applications | 17 |
Pending Applications | 48 |
Abandoned Applications | 31 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3775523
[patent_doc_number] => 05742761
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Apparatus for adapting message protocols for a switch network and a bus'
[patent_app_type] => 1
[patent_app_number] => 8/800070
[patent_app_country] => US
[patent_app_date] => 1997-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 35
[patent_no_of_words] => 22695
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742761.pdf
[firstpage_image] =>[orig_patent_app_number] => 800070
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/800070 | Apparatus for adapting message protocols for a switch network and a bus | Feb 11, 1997 | Issued |
Array
(
[id] => 3761404
[patent_doc_number] => 05717946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Data processor'
[patent_app_type] => 1
[patent_app_number] => 8/783531
[patent_app_country] => US
[patent_app_date] => 1997-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 100
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717946.pdf
[firstpage_image] =>[orig_patent_app_number] => 783531
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/783531 | Data processor | Jan 13, 1997 | Issued |
Array
(
[id] => 3852949
[patent_doc_number] => 05761691
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Linearly addressable microprocessor cache'
[patent_app_type] => 1
[patent_app_number] => 8/780263
[patent_app_country] => US
[patent_app_date] => 1997-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 9098
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[patent_words_short_claim] => 195
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[patent_no_of_assignments] => 0
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[pdf_file] => patents/05/761/05761691.pdf
[firstpage_image] =>[orig_patent_app_number] => 780263
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/780263 | Linearly addressable microprocessor cache | Jan 7, 1997 | Issued |
Array
(
[id] => 3670758
[patent_doc_number] => 05659763
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Apparatus and method for reducing power consumption by peripheral devices by controlling the interconnection of power supplies'
[patent_app_type] => 1
[patent_app_number] => 8/751275
[patent_app_country] => US
[patent_app_date] => 1996-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 2438
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[pdf_file] => patents/05/659/05659763.pdf
[firstpage_image] =>[orig_patent_app_number] => 751275
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/751275 | Apparatus and method for reducing power consumption by peripheral devices by controlling the interconnection of power supplies | Nov 17, 1996 | Issued |
Array
(
[id] => 3860867
[patent_doc_number] => 05745884
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'System and method for billing data grade network use on a per connection basis'
[patent_app_type] => 1
[patent_app_number] => 8/733942
[patent_app_country] => US
[patent_app_date] => 1996-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 6926
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/745/05745884.pdf
[firstpage_image] =>[orig_patent_app_number] => 733942
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/733942 | System and method for billing data grade network use on a per connection basis | Oct 20, 1996 | Issued |
Array
(
[id] => 3900405
[patent_doc_number] => 05806049
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Data processing system for global assessment of investment opportunity and cost'
[patent_app_type] => 1
[patent_app_number] => 8/893579
[patent_app_country] => US
[patent_app_date] => 1996-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3899
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[pdf_file] => patents/05/806/05806049.pdf
[firstpage_image] =>[orig_patent_app_number] => 893579
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893579 | Data processing system for global assessment of investment opportunity and cost | Sep 29, 1996 | Issued |
Array
(
[id] => 3804075
[patent_doc_number] => 05737628
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Multiprocessor computer system with interleaved processing element nodes'
[patent_app_type] => 1
[patent_app_number] => 8/662868
[patent_app_country] => US
[patent_app_date] => 1996-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
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[patent_no_of_words] => 11499
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[pdf_file] => patents/05/737/05737628.pdf
[firstpage_image] =>[orig_patent_app_number] => 662868
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/662868 | Multiprocessor computer system with interleaved processing element nodes | Jun 11, 1996 | Issued |
Array
(
[id] => 3677133
[patent_doc_number] => 05598575
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Multiprocessor data memory sharing system in which access to the data memory is determined by the control processor\'s access to the program memory'
[patent_app_type] => 1
[patent_app_number] => 8/626911
[patent_app_country] => US
[patent_app_date] => 1996-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/05/598/05598575.pdf
[firstpage_image] =>[orig_patent_app_number] => 626911
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/626911 | Multiprocessor data memory sharing system in which access to the data memory is determined by the control processor's access to the program memory | Apr 14, 1996 | Issued |
Array
(
[id] => 3893622
[patent_doc_number] => 05764910
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Method and apparatus for encoding and using network resource locators'
[patent_app_type] => 1
[patent_app_number] => 8/626601
[patent_app_country] => US
[patent_app_date] => 1996-04-02
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[pdf_file] => patents/05/764/05764910.pdf
[firstpage_image] =>[orig_patent_app_number] => 626601
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/626601 | Method and apparatus for encoding and using network resource locators | Apr 1, 1996 | Issued |
Array
(
[id] => 3893622
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[firstpage_image] =>[orig_patent_app_number] => 626601
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/626601 | Method and apparatus for encoding and using network resource locators | Apr 1, 1996 | Issued |
Array
(
[id] => 3922757
[patent_doc_number] => 05752259
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache'
[patent_app_type] => 1
[patent_app_number] => 8/621960
[patent_app_country] => US
[patent_app_date] => 1996-03-26
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[pdf_file] => patents/05/752/05752259.pdf
[firstpage_image] =>[orig_patent_app_number] => 621960
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/621960 | Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache | Mar 25, 1996 | Issued |
Array
(
[id] => 3898028
[patent_doc_number] => 05748900
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Adaptive congestion control mechanism for modular computer networks'
[patent_app_type] => 1
[patent_app_number] => 8/615700
[patent_app_country] => US
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[pdf_file] => patents/05/748/05748900.pdf
[firstpage_image] =>[orig_patent_app_number] => 615700
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/615700 | Adaptive congestion control mechanism for modular computer networks | Mar 12, 1996 | Issued |
Array
(
[id] => 3887740
[patent_doc_number] => 05838942
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Panic trap system and method'
[patent_app_type] => 1
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 609807
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/609807 | Panic trap system and method | Feb 29, 1996 | Issued |
Array
(
[id] => 3673089
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Resource management system and method'
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[firstpage_image] =>[orig_patent_app_number] => 583484
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/583484 | Resource management system and method | Jan 4, 1996 | Issued |
Array
(
[id] => 3812449
[patent_doc_number] => 05781801
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Method and apparatus for receive buffer management in multi-sender communication systems'
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[patent_app_number] => 8/580011
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[firstpage_image] =>[orig_patent_app_number] => 580011
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/580011 | Method and apparatus for receive buffer management in multi-sender communication systems | Dec 19, 1995 | Issued |
08/575189 | MULTI-CIRCUIT PROCESSOR DEVICE AND METHOD | Dec 19, 1995 | Abandoned |
Array
(
[id] => 3671127
[patent_doc_number] => 05659789
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU'
[patent_app_type] => 1
[patent_app_number] => 8/573963
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/448361 | Network element managing system | Dec 6, 1995 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/561760 | Data processing apparatus and method for making same | Nov 21, 1995 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1998-03-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/559659 | Interrupt coprocessor configured to process interrupts in a computer system | Nov 19, 1995 | Issued |