Joseph R Haley

Array ( [id] => 4264876 [patent_doc_number] => 06204541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/559141 [patent_app_country] => US [patent_app_date] => 2000-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5607 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204541.pdf [firstpage_image] =>[orig_patent_app_number] => 559141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4195085 [patent_doc_number] => 06153921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Diode device' [patent_app_type] => 1 [patent_app_number] => 9/434283 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1892 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153921.pdf [firstpage_image] =>[orig_patent_app_number] => 434283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4243932 [patent_doc_number] => 06091110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'MOSFET device having recessed gate-drain shield and method' [patent_app_type] => 1 [patent_app_number] => 9/430530 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 1722 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091110.pdf [firstpage_image] =>[orig_patent_app_number] => 430530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4360894 [patent_doc_number] => 06218723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Integrated capacitor with high voltage linearity and low series resistance' [patent_app_type] => 1 [patent_app_number] => 9/390862 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2715 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218723.pdf [firstpage_image] =>[orig_patent_app_number] => 390862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159079 [patent_doc_number] => 06124626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Capacitor structures formed using excess oxygen containing material provided relative to electrodes thereof' [patent_app_type] => 1 [patent_app_number] => 9/383052 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3967 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124626.pdf [firstpage_image] =>[orig_patent_app_number] => 383052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4210080 [patent_doc_number] => 06078087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'SRAM memory device with improved performance' [patent_app_type] => 1 [patent_app_number] => 9/379230 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4569 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078087.pdf [firstpage_image] =>[orig_patent_app_number] => 379230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4222936 [patent_doc_number] => 06087709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby' [patent_app_type] => 1 [patent_app_number] => 9/379391 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3417 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087709.pdf [firstpage_image] =>[orig_patent_app_number] => 379391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4238975 [patent_doc_number] => 06075259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Power semiconductor devices that utilize buried insulating regions to achieve higher than parallel-plane breakdown voltages' [patent_app_type] => 1 [patent_app_number] => 9/352392 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6824 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075259.pdf [firstpage_image] =>[orig_patent_app_number] => 352392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309248 [patent_doc_number] => 06188088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Electrostatic discharge protection for analog switches' [patent_app_type] => 1 [patent_app_number] => 9/349291 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1460 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188088.pdf [firstpage_image] =>[orig_patent_app_number] => 349291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4189472 [patent_doc_number] => 06150702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Lateral high-voltage semiconductor device having an outwardly extended electrode' [patent_app_type] => 1 [patent_app_number] => 9/340721 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150702.pdf [firstpage_image] =>[orig_patent_app_number] => 340721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159091 [patent_doc_number] => 06124627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region' [patent_app_type] => 1 [patent_app_number] => 9/334991 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 18 [patent_no_of_words] => 3951 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124627.pdf [firstpage_image] =>[orig_patent_app_number] => 334991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4264855 [patent_doc_number] => 06204540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Memory cell structure of a mask programmable read only memory with ion-implantation stopper films' [patent_app_type] => 1 [patent_app_number] => 9/333992 [patent_app_country] => US [patent_app_date] => 1999-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 20004 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204540.pdf [firstpage_image] =>[orig_patent_app_number] => 333992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309366 [patent_doc_number] => 06188096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'DRAM cell capacitor having increased trench capacitance' [patent_app_type] => 1 [patent_app_number] => 9/328961 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 26 [patent_no_of_words] => 3924 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188096.pdf [firstpage_image] =>[orig_patent_app_number] => 328961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4242328 [patent_doc_number] => 06144053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor device having a capacitor with a high dielectric constant film' [patent_app_type] => 1 [patent_app_number] => 9/327422 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 5136 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144053.pdf [firstpage_image] =>[orig_patent_app_number] => 327422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4108428 [patent_doc_number] => 06100571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Fet having non-overlapping field control electrode between gate and drain' [patent_app_type] => 1 [patent_app_number] => 9/326702 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 5750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100571.pdf [firstpage_image] =>[orig_patent_app_number] => 326702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4300994 [patent_doc_number] => 06184553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/325772 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 51 [patent_no_of_words] => 17482 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184553.pdf [firstpage_image] =>[orig_patent_app_number] => 325772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4301062 [patent_doc_number] => 06184558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Comparator having reduced offset voltage' [patent_app_type] => 1 [patent_app_number] => 9/323503 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4878 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184558.pdf [firstpage_image] =>[orig_patent_app_number] => 323503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423600 [patent_doc_number] => 06177703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method and apparatus for producing a single polysilicon flash EEPROM having a select transistor and a floating gate transistor' [patent_app_type] => 1 [patent_app_number] => 9/321792 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4019 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177703.pdf [firstpage_image] =>[orig_patent_app_number] => 321792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239190 [patent_doc_number] => 06075274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Semiconductor devices having gate stack with improved sidewall integrity' [patent_app_type] => 1 [patent_app_number] => 9/323178 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2658 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075274.pdf [firstpage_image] =>[orig_patent_app_number] => 323178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4319840 [patent_doc_number] => 06242792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Semiconductor device having oblique portion as reflection' [patent_app_type] => 1 [patent_app_number] => 9/315132 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 11632 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242792.pdf [firstpage_image] =>[orig_patent_app_number] => 315132 [rel_patent_id] =>[rel_patent_doc_number] =>)