Andrew J Oyer
Examiner (ID: 2471, Phone: (571)270-0347 , Office: P/1767 )
Most Active Art Unit | 1767 |
Art Unit(s) | 1767 |
Total Applications | 638 |
Issued Applications | 430 |
Pending Applications | 78 |
Abandoned Applications | 130 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4145220
[patent_doc_number] => 06063641
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Method of measuring electrical characteristics of semiconductor circuit in wafer state and semiconductor device for the same'
[patent_app_type] => 1
[patent_app_number] => 9/401800
[patent_app_country] => US
[patent_app_date] => 1999-09-22
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[pdf_file] => patents/06/063/06063641.pdf
[firstpage_image] =>[orig_patent_app_number] => 401800
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/401800 | Method of measuring electrical characteristics of semiconductor circuit in wafer state and semiconductor device for the same | Sep 21, 1999 | Issued |
Array
(
[id] => 4113642
[patent_doc_number] => 06046067
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Micromechanical device and method for its production'
[patent_app_type] => 1
[patent_app_number] => 9/283533
[patent_app_country] => US
[patent_app_date] => 1999-04-01
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[pdf_file] => patents/06/046/06046067.pdf
[firstpage_image] =>[orig_patent_app_number] => 283533
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/283533 | Micromechanical device and method for its production | Mar 31, 1999 | Issued |
Array
(
[id] => 4176641
[patent_doc_number] => 06140683
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection'
[patent_app_type] => 1
[patent_app_number] => 9/251015
[patent_app_country] => US
[patent_app_date] => 1999-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2494
[patent_no_of_claims] => 6
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[pdf_file] => patents/06/140/06140683.pdf
[firstpage_image] =>[orig_patent_app_number] => 251015
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/251015 | Efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection | Feb 15, 1999 | Issued |
Array
(
[id] => 3944896
[patent_doc_number] => 05953578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Global planarization method using plasma etching'
[patent_app_type] => 1
[patent_app_number] => 9/149240
[patent_app_country] => US
[patent_app_date] => 1998-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1075
[patent_no_of_claims] => 16
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[pdf_file] => patents/05/953/05953578.pdf
[firstpage_image] =>[orig_patent_app_number] => 149240
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/149240 | Global planarization method using plasma etching | Sep 7, 1998 | Issued |
Array
(
[id] => 4194733
[patent_doc_number] => 06153897
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Heterojunction compound semiconductor device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/145287
[patent_app_country] => US
[patent_app_date] => 1998-09-02
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 5282
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[pdf_file] => patents/06/153/06153897.pdf
[firstpage_image] =>[orig_patent_app_number] => 145287
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/145287 | Heterojunction compound semiconductor device and method of manufacturing the same | Sep 1, 1998 | Issued |
Array
(
[id] => 4132680
[patent_doc_number] => 06127725
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Thin film electronics on insulator on metal'
[patent_app_type] => 1
[patent_app_number] => 9/128107
[patent_app_country] => US
[patent_app_date] => 1998-08-03
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[pdf_file] => patents/06/127/06127725.pdf
[firstpage_image] =>[orig_patent_app_number] => 128107
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/128107 | Thin film electronics on insulator on metal | Aug 2, 1998 | Issued |
Array
(
[id] => 4130913
[patent_doc_number] => 06146941
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Method for fabricating a capacitor in a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/128221
[patent_app_country] => US
[patent_app_date] => 1998-08-03
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[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3254
[patent_no_of_claims] => 23
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[pdf_file] => patents/06/146/06146941.pdf
[firstpage_image] =>[orig_patent_app_number] => 128221
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/128221 | Method for fabricating a capacitor in a semiconductor device | Aug 2, 1998 | Issued |
Array
(
[id] => 4004058
[patent_doc_number] => 05960273
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Method of manufacturing a semiconductor device including a bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 9/124507
[patent_app_country] => US
[patent_app_date] => 1998-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
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[pdf_file] => patents/05/960/05960273.pdf
[firstpage_image] =>[orig_patent_app_number] => 124507
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/124507 | Method of manufacturing a semiconductor device including a bipolar transistor | Jul 28, 1998 | Issued |
Array
(
[id] => 4108564
[patent_doc_number] => 06100579
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Insulating film for use in semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/983010
[patent_app_country] => US
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[pdf_file] => patents/06/100/06100579.pdf
[firstpage_image] =>[orig_patent_app_number] => 983010
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/983010 | Insulating film for use in semiconductor device | Jul 1, 1998 | Issued |
09/103860 | METHOD OF FORMING INTER-METAL DIELECTRIC LAYER FOR WVIA PROCESS | Jun 23, 1998 | Issued |
Array
(
[id] => 4077481
[patent_doc_number] => 06024772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Solid electrolyte capacitor and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/093620
[patent_app_country] => US
[patent_app_date] => 1998-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/024/06024772.pdf
[firstpage_image] =>[orig_patent_app_number] => 093620
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/093620 | Solid electrolyte capacitor and method of manufacturing the same | Jun 8, 1998 | Issued |
Array
(
[id] => 4197530
[patent_doc_number] => 06013552
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-11
[patent_title] => 'Method of manufacturing a split-gate flash memory cell'
[patent_app_type] => 1
[patent_app_number] => 9/090227
[patent_app_country] => US
[patent_app_date] => 1998-06-04
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[pdf_file] => patents/06/013/06013552.pdf
[firstpage_image] =>[orig_patent_app_number] => 090227
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/090227 | Method of manufacturing a split-gate flash memory cell | Jun 3, 1998 | Issued |
Array
(
[id] => 4169067
[patent_doc_number] => 06140184
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Method of changing the power dissipation across an array of transistors'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 088027
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/088027 | Method of changing the power dissipation across an array of transistors | May 31, 1998 | Issued |
Array
(
[id] => 4097907
[patent_doc_number] => 06048773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Methods of forming bipolar junction transistors having preferred base electrode extensions and transistors formed thereby'
[patent_app_type] => 1
[patent_app_number] => 9/085777
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/085777 | Methods of forming bipolar junction transistors having preferred base electrode extensions and transistors formed thereby | May 27, 1998 | Issued |
Array
(
[id] => 4130658
[patent_doc_number] => 06121060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Method of measuring a concentration profile'
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[patent_app_number] => 9/084206
[patent_app_country] => US
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[pdf_file] => patents/06/121/06121060.pdf
[firstpage_image] =>[orig_patent_app_number] => 084206
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/084206 | Method of measuring a concentration profile | May 25, 1998 | Issued |
Array
(
[id] => 4101281
[patent_doc_number] => 06097042
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Symmetrical multi-layer metal logic array employing single gate connection pad region transistors'
[patent_app_type] => 1
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[pdf_file] => patents/06/097/06097042.pdf
[firstpage_image] =>[orig_patent_app_number] => 083950
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/083950 | Symmetrical multi-layer metal logic array employing single gate connection pad region transistors | May 25, 1998 | Issued |
Array
(
[id] => 4253379
[patent_doc_number] => 06137157
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Semiconductor memory array having shared column redundancy programming'
[patent_app_type] => 1
[patent_app_number] => 9/083327
[patent_app_country] => US
[patent_app_date] => 1998-05-21
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[pdf_file] => patents/06/137/06137157.pdf
[firstpage_image] =>[orig_patent_app_number] => 083327
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/083327 | Semiconductor memory array having shared column redundancy programming | May 20, 1998 | Issued |
Array
(
[id] => 4102382
[patent_doc_number] => 06051469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Method of fabricating bit line'
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[firstpage_image] =>[orig_patent_app_number] => 082660
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/082660 | Method of fabricating bit line | May 20, 1998 | Issued |
Array
(
[id] => 4124376
[patent_doc_number] => 06127193
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[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure'
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[pdf_file] => patents/06/127/06127193.pdf
[firstpage_image] =>[orig_patent_app_number] => 080917
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/080917 | Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure | May 17, 1998 | Issued |
Array
(
[id] => 4076098
[patent_doc_number] => 06069399
[patent_country] => US
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[patent_issue_date] => 2000-05-30
[patent_title] => 'Vertical bipolar semiconductor power transistor with an interdigitized geometry, with optimization of the base-to-emitter potential difference'
[patent_app_type] => 1
[patent_app_number] => 9/079827
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[pdf_file] => patents/06/069/06069399.pdf
[firstpage_image] =>[orig_patent_app_number] => 079827
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/079827 | Vertical bipolar semiconductor power transistor with an interdigitized geometry, with optimization of the base-to-emitter potential difference | May 14, 1998 | Issued |