Randy A Flynn

Array ( [id] => 7148835 [patent_doc_number] => 20050120173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Device and method for performing information processing using plurality of processors' [patent_app_type] => utility [patent_app_number] => 10/767074 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 23169 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20050120173.pdf [firstpage_image] =>[orig_patent_app_number] => 10767074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 675940 [patent_doc_number] => 07093065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Random access memory initialization' [patent_app_type] => utility [patent_app_number] => 10/736057 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1294 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/093/07093065.pdf [firstpage_image] =>[orig_patent_app_number] => 10736057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6919780 [patent_doc_number] => 20050097266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Chaining of blocks for optimal performance with DASD (Direct Access Storage Devices) free nonvolatile updates' [patent_app_type] => utility [patent_app_number] => 10/699149 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5138 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097266.pdf [firstpage_image] =>[orig_patent_app_number] => 10699149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 765246 [patent_doc_number] => 07017027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Address counter control system with path switching' [patent_app_type] => utility [patent_app_number] => 10/669303 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3937 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/017/07017027.pdf [firstpage_image] =>[orig_patent_app_number] => 10669303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 675931 [patent_doc_number] => 07093063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Data rewriting for flash memory' [patent_app_type] => utility [patent_app_number] => 10/665617 [patent_app_country] => US [patent_app_date] => 2003-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 13233 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/093/07093063.pdf [firstpage_image] =>[orig_patent_app_number] => 10665617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 705041 [patent_doc_number] => 07069380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'File access method in storage-device system, and programs for the file access' [patent_app_type] => utility [patent_app_number] => 10/653895 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9278 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069380.pdf [firstpage_image] =>[orig_patent_app_number] => 10653895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 749374 [patent_doc_number] => 07032088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Advanced memory management architecture for large data volumes' [patent_app_type] => utility [patent_app_number] => 10/636434 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4557 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032088.pdf [firstpage_image] =>[orig_patent_app_number] => 10636434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7123733 [patent_doc_number] => 20050015562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Block cache size management via virtual memory manager feedback' [patent_app_type] => utility [patent_app_number] => 10/620938 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7642 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20050015562.pdf [firstpage_image] =>[orig_patent_app_number] => 10620938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 659354 [patent_doc_number] => 07111146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine' [patent_app_type] => utility [patent_app_number] => 10/607934 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5494 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111146.pdf [firstpage_image] =>[orig_patent_app_number] => 10607934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7390950 [patent_doc_number] => 20040083227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Implementation of a memory efficient matrix' [patent_app_type] => new [patent_app_number] => 10/280457 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6721 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083227.pdf [firstpage_image] =>[orig_patent_app_number] => 10280457 [rel_patent_id] =>[rel_patent_doc_number] =>)