Natasha W Cosme

Array ( [id] => 10544503 [patent_doc_number] => 09269636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'High quality dielectric for hi-k last replacement gate transistors' [patent_app_type] => utility [patent_app_number] => 14/575490 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2537 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14575490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10302661 [patent_doc_number] => 20150187661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'DUAL LAYER HARDMASK FOR EMBEDDED EPI GROWTH' [patent_app_type] => utility [patent_app_number] => 14/575512 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14575512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10028875 [patent_doc_number] => 09070785 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-30 [patent_title] => 'High-k / metal gate CMOS transistors with TiN gates' [patent_app_type] => utility [patent_app_number] => 14/567507 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 5572 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9864829 [patent_doc_number] => 20150044848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'HIGH VOLTAGE HYBRID POLYMERIC-CERAMIC DIELECTRIC CAPACITOR' [patent_app_type] => utility [patent_app_number] => 14/504938 [patent_app_country] => US [patent_app_date] => 2014-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3529 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14504938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9792813 [patent_doc_number] => 20150004757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/490391 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5068 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14490391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9917322 [patent_doc_number] => 20150072527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'METHOD FOR PATTERNING A PLURALITY OF FEATURES FOR FIN-LIKE FIELD-EFFECT TRANSISTOR (FINFET) DEVICES' [patent_app_type] => utility [patent_app_number] => 14/485168 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14485168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10042082 [patent_doc_number] => 09082795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Precursor composition of oxide semiconductor and thin film transistor substrate including oxide semiconductor' [patent_app_type] => utility [patent_app_number] => 14/477587 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5955 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10047450 [patent_doc_number] => 09087855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/474516 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 59 [patent_no_of_words] => 27616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14474516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10929884 [patent_doc_number] => 20140332905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/444200 [patent_app_country] => US [patent_app_date] => 2014-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5345 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14444200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11201075 [patent_doc_number] => 09431296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Structure and method to form liner silicide with improved contact resistance and reliablity' [patent_app_type] => utility [patent_app_number] => 14/315514 [patent_app_country] => US [patent_app_date] => 2014-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7348 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14315514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10394944 [patent_doc_number] => 20150279950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/315170 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6418 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14315170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10943592 [patent_doc_number] => 20140346613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'METHODS OF FABRICATING FIN STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/292443 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4787 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14292443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9716119 [patent_doc_number] => 20140251817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'METAL CONTACT SCHEME AND PASSIVATION SCHEME FOR SOLAR CELLS' [patent_app_type] => utility [patent_app_number] => 14/286665 [patent_app_country] => US [patent_app_date] => 2014-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17154 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14286665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9699068 [patent_doc_number] => 20140248753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'ANALOG TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/273938 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10597486 [patent_doc_number] => 09318582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Method of preventing epitaxy creeping under the spacer' [patent_app_type] => utility [patent_app_number] => 14/215564 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5664 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14215564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10525712 [patent_doc_number] => 09252233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Air-gap offset spacer in FinFET structure' [patent_app_type] => utility [patent_app_number] => 14/205971 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10162311 [patent_doc_number] => 09193525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Apparatus for handling electronic components' [patent_app_type] => utility [patent_app_number] => 14/205607 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2717 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10351115 [patent_doc_number] => 20150236120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'NANOWIRE TRANSISTOR STRUCTURES WITH MERGED SOURCE/DRAIN REGIONS USING AUXILIARY PILLARS' [patent_app_type] => utility [patent_app_number] => 14/181564 [patent_app_country] => US [patent_app_date] => 2014-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14181564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9950980 [patent_doc_number] => 08999766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'ESD/antenna diodes for through-silicon vias' [patent_app_type] => utility [patent_app_number] => 14/133369 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9853 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9277945 [patent_doc_number] => 20140027913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'SEMICONDUCTOR STRUCTURES COMPRISING CONDUCTIVE MATERIAL LINING OPENINGS IN AN INSULATIVE MATERIAL' [patent_app_type] => utility [patent_app_number] => 14/037633 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5643 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037633 [rel_patent_id] =>[rel_patent_doc_number] =>)