Search

Laura Mary Menz

Examiner (ID: 3662)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2142
Issued Applications
1843
Pending Applications
83
Abandoned Applications
195

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4236453 [patent_doc_number] => 06041391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Storage device and method for data sharing' [patent_app_type] => 1 [patent_app_number] => 9/315819 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 8608 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041391.pdf [firstpage_image] =>[orig_patent_app_number] => 315819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315819
Storage device and method for data sharing May 20, 1999 Issued
Array ( [id] => 3967215 [patent_doc_number] => 05983317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Storage device and method for data sharing' [patent_app_type] => 1 [patent_app_number] => 9/256472 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 8596 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983317.pdf [firstpage_image] =>[orig_patent_app_number] => 256472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256472
Storage device and method for data sharing Feb 22, 1999 Issued
Array ( [id] => 4121389 [patent_doc_number] => 06023749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Object and method for providing efficient multi-user access to shared operating system kernal code using instancing' [patent_app_type] => 1 [patent_app_number] => 9/236928 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2630 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023749.pdf [firstpage_image] =>[orig_patent_app_number] => 236928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236928
Object and method for providing efficient multi-user access to shared operating system kernal code using instancing Jan 24, 1999 Issued
Array ( [id] => 3971156 [patent_doc_number] => 06000015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache' [patent_app_type] => 1 [patent_app_number] => 9/232198 [patent_app_country] => US [patent_app_date] => 1999-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7451 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000015.pdf [firstpage_image] =>[orig_patent_app_number] => 232198 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232198
Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache Jan 15, 1999 Issued
Array ( [id] => 3971033 [patent_doc_number] => 06000007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Caching in a multi-processor computer system' [patent_app_type] => 1 [patent_app_number] => 9/080893 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7782 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000007.pdf [firstpage_image] =>[orig_patent_app_number] => 080893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080893
Caching in a multi-processor computer system May 17, 1998 Issued
Array ( [id] => 3932919 [patent_doc_number] => 06003121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Single and multiple channel memory detection and sizing' [patent_app_type] => 1 [patent_app_number] => 9/080872 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2515 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003121.pdf [firstpage_image] =>[orig_patent_app_number] => 080872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080872
Single and multiple channel memory detection and sizing May 17, 1998 Issued
Array ( [id] => 4103717 [patent_doc_number] => 06026468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method of controlling magnetic tape unit' [patent_app_type] => 1 [patent_app_number] => 9/013050 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 39 [patent_no_of_words] => 11247 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026468.pdf [firstpage_image] =>[orig_patent_app_number] => 013050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013050
Method of controlling magnetic tape unit Jan 25, 1998 Issued
Array ( [id] => 4160478 [patent_doc_number] => 06061764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions' [patent_app_type] => 1 [patent_app_number] => 9/013097 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5769 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061764.pdf [firstpage_image] =>[orig_patent_app_number] => 013097 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013097
Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions Jan 25, 1998 Issued
Array ( [id] => 4133125 [patent_doc_number] => 06047354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Data processor for implementing virtual pages using a cache and register' [patent_app_type] => 1 [patent_app_number] => 9/007249 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 16188 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047354.pdf [firstpage_image] =>[orig_patent_app_number] => 007249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007249
Data processor for implementing virtual pages using a cache and register Jan 13, 1998 Issued
Array ( [id] => 4026823 [patent_doc_number] => 05890197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Semiconductor memory device having split transfer function' [patent_app_type] => 1 [patent_app_number] => 8/989789 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 14808 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 534 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890197.pdf [firstpage_image] =>[orig_patent_app_number] => 989789 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989789
Semiconductor memory device having split transfer function Dec 11, 1997 Issued
Array ( [id] => 3909769 [patent_doc_number] => 05835719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Apparatus and method for remote wake-up in system having interlinked networks' [patent_app_type] => 1 [patent_app_number] => 8/972093 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3231 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835719.pdf [firstpage_image] =>[orig_patent_app_number] => 972093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972093
Apparatus and method for remote wake-up in system having interlinked networks Nov 16, 1997 Issued
Array ( [id] => 4200131 [patent_doc_number] => 06021481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Effective-to-real address cache managing apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/966706 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4914 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021481.pdf [firstpage_image] =>[orig_patent_app_number] => 966706 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966706
Effective-to-real address cache managing apparatus and method Nov 9, 1997 Issued
Array ( [id] => 4167286 [patent_doc_number] => 06065102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Fault tolerant multiple client memory arbitration system capable of operating multiple configuration types' [patent_app_type] => 1 [patent_app_number] => 8/965718 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 15944 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065102.pdf [firstpage_image] =>[orig_patent_app_number] => 965718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/965718
Fault tolerant multiple client memory arbitration system capable of operating multiple configuration types Nov 6, 1997 Issued
Array ( [id] => 4151626 [patent_doc_number] => 06035368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Protection method against eeprom-directed intrusion into a mobile communication device that has a processor, and a device having such protection mechanism' [patent_app_type] => 1 [patent_app_number] => 8/966224 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2138 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035368.pdf [firstpage_image] =>[orig_patent_app_number] => 966224 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966224
Protection method against eeprom-directed intrusion into a mobile communication device that has a processor, and a device having such protection mechanism Nov 6, 1997 Issued
Array ( [id] => 4256906 [patent_doc_number] => 06081870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method and apparatus to achieve fast suspend in flash memories' [patent_app_type] => 1 [patent_app_number] => 8/965253 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2894 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081870.pdf [firstpage_image] =>[orig_patent_app_number] => 965253 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/965253
Method and apparatus to achieve fast suspend in flash memories Nov 5, 1997 Issued
Array ( [id] => 3973399 [patent_doc_number] => 05978889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception' [patent_app_type] => 1 [patent_app_number] => 8/964771 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 5625 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978889.pdf [firstpage_image] =>[orig_patent_app_number] => 964771 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964771
Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception Nov 4, 1997 Issued
Array ( [id] => 4240166 [patent_doc_number] => 06012131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'High speed translation lookaside buffer employing content address memory' [patent_app_type] => 1 [patent_app_number] => 8/964903 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4854 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012131.pdf [firstpage_image] =>[orig_patent_app_number] => 964903 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964903
High speed translation lookaside buffer employing content address memory Nov 4, 1997 Issued
Array ( [id] => 4103703 [patent_doc_number] => 06026467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Content-addressable memory implemented with a memory management unit' [patent_app_type] => 1 [patent_app_number] => 8/942190 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3149 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026467.pdf [firstpage_image] =>[orig_patent_app_number] => 942190 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942190
Content-addressable memory implemented with a memory management unit Sep 30, 1997 Issued
Array ( [id] => 4252403 [patent_doc_number] => 06076139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Multimedia computer architecture with multi-channel concurrent memory access' [patent_app_type] => 1 [patent_app_number] => 8/940914 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6013 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076139.pdf [firstpage_image] =>[orig_patent_app_number] => 940914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940914
Multimedia computer architecture with multi-channel concurrent memory access Sep 29, 1997 Issued
Array ( [id] => 3954812 [patent_doc_number] => 05900012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Storage device having varying access times and a superscalar microprocessor employing the same' [patent_app_type] => 1 [patent_app_number] => 8/933270 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5661 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900012.pdf [firstpage_image] =>[orig_patent_app_number] => 933270 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933270
Storage device having varying access times and a superscalar microprocessor employing the same Sep 17, 1997 Issued
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