Young Whang
Examiner (ID: 3798)
Most Active Art Unit | 2103 |
Art Unit(s) | 2103 |
Total Applications | 382 |
Issued Applications | 354 |
Pending Applications | 5 |
Abandoned Applications | 23 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4357327
[patent_doc_number] => 06190982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Method of fabricating a MOS transistor on a semiconductor wafer'
[patent_app_type] => 1
[patent_app_number] => 9/492670
[patent_app_country] => US
[patent_app_date] => 2000-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 1945
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/190/06190982.pdf
[firstpage_image] =>[orig_patent_app_number] => 492670
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/492670 | Method of fabricating a MOS transistor on a semiconductor wafer | Jan 27, 2000 | Issued |
Array
(
[id] => 4124638
[patent_doc_number] => 06127212
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Method of forming a CMOS transistor'
[patent_app_type] => 1
[patent_app_number] => 9/488811
[patent_app_country] => US
[patent_app_date] => 2000-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2780
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/127/06127212.pdf
[firstpage_image] =>[orig_patent_app_number] => 488811
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/488811 | Method of forming a CMOS transistor | Jan 20, 2000 | Issued |
Array
(
[id] => 4131657
[patent_doc_number] => 06146988
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Method of making a semiconductor device comprising copper interconnects with reduced in-line copper diffusion'
[patent_app_type] => 1
[patent_app_number] => 9/477820
[patent_app_country] => US
[patent_app_date] => 2000-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3811
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/146/06146988.pdf
[firstpage_image] =>[orig_patent_app_number] => 477820
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/477820 | Method of making a semiconductor device comprising copper interconnects with reduced in-line copper diffusion | Jan 4, 2000 | Issued |
Array
(
[id] => 4086361
[patent_doc_number] => 06133057
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Method of fabricating field emission arrays employing a hard mask to define column lines and another mask to define emitter tips and resistors'
[patent_app_type] => 1
[patent_app_number] => 9/472571
[patent_app_country] => US
[patent_app_date] => 1999-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 4515
[patent_no_of_claims] => 59
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/133/06133057.pdf
[firstpage_image] =>[orig_patent_app_number] => 472571
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/472571 | Method of fabricating field emission arrays employing a hard mask to define column lines and another mask to define emitter tips and resistors | Dec 26, 1999 | Issued |
Array
(
[id] => 4153039
[patent_doc_number] => 06107140
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Method of patterning gate electrode conductor with ultra-thin gate oxide'
[patent_app_type] => 1
[patent_app_number] => 9/467131
[patent_app_country] => US
[patent_app_date] => 1999-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2103
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/107/06107140.pdf
[firstpage_image] =>[orig_patent_app_number] => 467131
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/467131 | Method of patterning gate electrode conductor with ultra-thin gate oxide | Dec 19, 1999 | Issued |
Array
(
[id] => 4237631
[patent_doc_number] => 06090707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Method of forming a conductive silicide layer on a silicon comprising substrate and method of forming a conductive silicide contact'
[patent_app_type] => 1
[patent_app_number] => 9/389535
[patent_app_country] => US
[patent_app_date] => 1999-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2836
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/090/06090707.pdf
[firstpage_image] =>[orig_patent_app_number] => 389535
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/389535 | Method of forming a conductive silicide layer on a silicon comprising substrate and method of forming a conductive silicide contact | Sep 1, 1999 | Issued |
Array
(
[id] => 4183013
[patent_doc_number] => 06150277
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Method of making an oxide structure having a finely calibrated thickness'
[patent_app_type] => 1
[patent_app_number] => 9/385156
[patent_app_country] => US
[patent_app_date] => 1999-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 3726
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/150/06150277.pdf
[firstpage_image] =>[orig_patent_app_number] => 385156
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/385156 | Method of making an oxide structure having a finely calibrated thickness | Aug 29, 1999 | Issued |
Array
(
[id] => 4312619
[patent_doc_number] => 06242321
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Structure and fabrication method for non-planar memory elements'
[patent_app_type] => 1
[patent_app_number] => 9/303595
[patent_app_country] => US
[patent_app_date] => 1999-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 40
[patent_no_of_words] => 4301
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/242/06242321.pdf
[firstpage_image] =>[orig_patent_app_number] => 303595
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/303595 | Structure and fabrication method for non-planar memory elements | May 2, 1999 | Issued |
Array
(
[id] => 4116674
[patent_doc_number] => 06071777
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Method for a self-aligned select gate for a split-gate flash memory structure'
[patent_app_type] => 1
[patent_app_number] => 9/301324
[patent_app_country] => US
[patent_app_date] => 1999-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 2981
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/071/06071777.pdf
[firstpage_image] =>[orig_patent_app_number] => 301324
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/301324 | Method for a self-aligned select gate for a split-gate flash memory structure | Apr 28, 1999 | Issued |
Array
(
[id] => 4238672
[patent_doc_number] => 06080669
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Semiconductor interconnect interface processing by high pressure deposition'
[patent_app_type] => 1
[patent_app_number] => 9/225644
[patent_app_country] => US
[patent_app_date] => 1999-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2984
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/080/06080669.pdf
[firstpage_image] =>[orig_patent_app_number] => 225644
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225644 | Semiconductor interconnect interface processing by high pressure deposition | Jan 4, 1999 | Issued |
Array
(
[id] => 4294337
[patent_doc_number] => 06184112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile'
[patent_app_type] => 1
[patent_app_number] => 9/204998
[patent_app_country] => US
[patent_app_date] => 1998-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2148
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/184/06184112.pdf
[firstpage_image] =>[orig_patent_app_number] => 204998
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/204998 | Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile | Dec 1, 1998 | Issued |
Array
(
[id] => 4359372
[patent_doc_number] => 06169034
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Chemically removable Cu CMP slurry abrasive'
[patent_app_type] => 1
[patent_app_number] => 9/199352
[patent_app_country] => US
[patent_app_date] => 1998-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2783
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/169/06169034.pdf
[firstpage_image] =>[orig_patent_app_number] => 199352
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/199352 | Chemically removable Cu CMP slurry abrasive | Nov 24, 1998 | Issued |
Array
(
[id] => 4095223
[patent_doc_number] => 06096643
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Method of fabricating a semiconductor device having polysilicon line with extended silicide layer'
[patent_app_type] => 1
[patent_app_number] => 9/164956
[patent_app_country] => US
[patent_app_date] => 1998-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 3458
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/096/06096643.pdf
[firstpage_image] =>[orig_patent_app_number] => 164956
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164956 | Method of fabricating a semiconductor device having polysilicon line with extended silicide layer | Sep 30, 1998 | Issued |
Array
(
[id] => 4107945
[patent_doc_number] => 06057230
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Dry etching procedure and recipe for patterning of thin film copper layers'
[patent_app_type] => 1
[patent_app_number] => 9/156051
[patent_app_country] => US
[patent_app_date] => 1998-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2435
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/057/06057230.pdf
[firstpage_image] =>[orig_patent_app_number] => 156051
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/156051 | Dry etching procedure and recipe for patterning of thin film copper layers | Sep 16, 1998 | Issued |
Array
(
[id] => 4071418
[patent_doc_number] => 06069093
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-30
[patent_title] => 'Process of forming metal films and multi layer structure'
[patent_app_type] => 1
[patent_app_number] => 9/098731
[patent_app_country] => US
[patent_app_date] => 1998-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 4970
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/069/06069093.pdf
[firstpage_image] =>[orig_patent_app_number] => 098731
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/098731 | Process of forming metal films and multi layer structure | Jun 17, 1998 | Issued |
Array
(
[id] => 4170118
[patent_doc_number] => 06140256
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Method and device for treating semiconductor with treating gas while substrate is heated'
[patent_app_type] => 1
[patent_app_number] => 9/068975
[patent_app_country] => US
[patent_app_date] => 1998-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 5875
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 400
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/140/06140256.pdf
[firstpage_image] =>[orig_patent_app_number] => 068975
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/068975 | Method and device for treating semiconductor with treating gas while substrate is heated | May 21, 1998 | Issued |
Array
(
[id] => 4136450
[patent_doc_number] => 06015730
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Integration of SAC and salicide processes by combining hard mask and poly definition'
[patent_app_type] => 1
[patent_app_number] => 9/034926
[patent_app_country] => US
[patent_app_date] => 1998-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2455
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 327
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/015/06015730.pdf
[firstpage_image] =>[orig_patent_app_number] => 034926
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/034926 | Integration of SAC and salicide processes by combining hard mask and poly definition | Mar 4, 1998 | Issued |
Array
(
[id] => 4186359
[patent_doc_number] => 06093656
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/031169
[patent_app_country] => US
[patent_app_date] => 1998-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2120
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/093/06093656.pdf
[firstpage_image] =>[orig_patent_app_number] => 031169
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/031169 | Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device | Feb 25, 1998 | Issued |
Array
(
[id] => 4236505
[patent_doc_number] => 06080526
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Integration of low-k polymers into interlevel dielectrics using controlled electron-beam radiation'
[patent_app_type] => 1
[patent_app_number] => 9/028465
[patent_app_country] => US
[patent_app_date] => 1998-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6473
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/080/06080526.pdf
[firstpage_image] =>[orig_patent_app_number] => 028465
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/028465 | Integration of low-k polymers into interlevel dielectrics using controlled electron-beam radiation | Feb 23, 1998 | Issued |
Array
(
[id] => 4156137
[patent_doc_number] => 06156637
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Method of planarizing a semiconductor device by depositing a dielectric ply structure'
[patent_app_type] => 1
[patent_app_number] => 8/997403
[patent_app_country] => US
[patent_app_date] => 1997-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 4092
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/156/06156637.pdf
[firstpage_image] =>[orig_patent_app_number] => 997403
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997403 | Method of planarizing a semiconductor device by depositing a dielectric ply structure | Dec 22, 1997 | Issued |