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Douglas W Olms

Examiner (ID: 3855)

Most Active Art Unit
2603
Art Unit(s)
2732, 2603, 2306, 2607, 2305, 2302, 2604, 2661
Total Applications
652
Issued Applications
593
Pending Applications
19
Abandoned Applications
40

Applications

Application numberTitle of the applicationFiling DateStatus
09/008335 SEMICONDUCTOR DEVICE Jan 15, 1998 Issued
Array ( [id] => 4057305 [patent_doc_number] => 05932912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Semiconductor device having LDD structure with a recess in the source/drain region which is formed during the removal of a damaged layer' [patent_app_type] => 1 [patent_app_number] => 8/946390 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 65 [patent_no_of_words] => 20762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/932/05932912.pdf [firstpage_image] =>[orig_patent_app_number] => 946390 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946390
Semiconductor device having LDD structure with a recess in the source/drain region which is formed during the removal of a damaged layer Oct 6, 1997 Issued
Array ( [id] => 3926786 [patent_doc_number] => 05914511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Circuit and method for a folded bit line memory using trench plate capacitor cells with body bias contacts' [patent_app_type] => 1 [patent_app_number] => 8/944312 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 36 [patent_no_of_words] => 7637 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/914/05914511.pdf [firstpage_image] =>[orig_patent_app_number] => 944312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944312
Circuit and method for a folded bit line memory using trench plate capacitor cells with body bias contacts Oct 5, 1997 Issued
Array ( [id] => 3932767 [patent_doc_number] => 05877511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Single-electron controlling magnetoresistance element' [patent_app_type] => 1 [patent_app_number] => 8/940194 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 6811 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877511.pdf [firstpage_image] =>[orig_patent_app_number] => 940194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940194
Single-electron controlling magnetoresistance element Sep 28, 1997 Issued
Array ( [id] => 3953826 [patent_doc_number] => 05977598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'High load resistance implemented in a separate polysilicon layer with diffusion barrier therein for preventing load punch through therefrom' [patent_app_type] => 1 [patent_app_number] => 8/935869 [patent_app_country] => US [patent_app_date] => 1997-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3776 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977598.pdf [firstpage_image] =>[orig_patent_app_number] => 935869 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/935869
High load resistance implemented in a separate polysilicon layer with diffusion barrier therein for preventing load punch through therefrom Sep 22, 1997 Issued
Array ( [id] => 4031262 [patent_doc_number] => 05903011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Semiconductor device having monitor pattern formed therein' [patent_app_type] => 1 [patent_app_number] => 8/895044 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 6615 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903011.pdf [firstpage_image] =>[orig_patent_app_number] => 895044 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895044
Semiconductor device having monitor pattern formed therein Jul 15, 1997 Issued
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