![](/images/general/no_picture/200_user.png)
Derrick Edward Holland
Examiner (ID: 404, Phone: (571)272-3089 , Office: P/2912 )
Most Active Art Unit | 2912 |
Art Unit(s) | 2912 |
Total Applications | 3302 |
Issued Applications | 3253 |
Pending Applications | 21 |
Abandoned Applications | 28 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3590335
[patent_doc_number] => 05491803
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'Response resolver for associative memories and parallel processors'
[patent_app_type] => 1
[patent_app_number] => 8/431478
[patent_app_country] => US
[patent_app_date] => 1995-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3657
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/491/05491803.pdf
[firstpage_image] =>[orig_patent_app_number] => 431478
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/431478 | Response resolver for associative memories and parallel processors | Apr 30, 1995 | Issued |
Array
(
[id] => 3564504
[patent_doc_number] => 05493662
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Apparatus for enabling exchange of data of different lengths between memories of at least two computer systems'
[patent_app_type] => 1
[patent_app_number] => 8/395487
[patent_app_country] => US
[patent_app_date] => 1995-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2764
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/493/05493662.pdf
[firstpage_image] =>[orig_patent_app_number] => 395487
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/395487 | Apparatus for enabling exchange of data of different lengths between memories of at least two computer systems | Feb 26, 1995 | Issued |
Array
(
[id] => 3432407
[patent_doc_number] => 05479631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'System for designating real main storage addresses in instructions while dynamic address translation is on'
[patent_app_type] => 1
[patent_app_number] => 8/376543
[patent_app_country] => US
[patent_app_date] => 1995-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3650
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479631.pdf
[firstpage_image] =>[orig_patent_app_number] => 376543
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/376543 | System for designating real main storage addresses in instructions while dynamic address translation is on | Jan 22, 1995 | Issued |
Array
(
[id] => 3589036
[patent_doc_number] => 05524234
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Coherency for write-back cache in a system designed for write-through cache including write-back latency control'
[patent_app_type] => 1
[patent_app_number] => 8/365972
[patent_app_country] => US
[patent_app_date] => 1994-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6809
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/524/05524234.pdf
[firstpage_image] =>[orig_patent_app_number] => 365972
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/365972 | Coherency for write-back cache in a system designed for write-through cache including write-back latency control | Dec 27, 1994 | Issued |
Array
(
[id] => 3122660
[patent_doc_number] => 05465344
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-07
[patent_title] => 'Microprocessor with dual-port cache memory for reducing penalty of consecutive memory address accesses'
[patent_app_type] => 1
[patent_app_number] => 8/352445
[patent_app_country] => US
[patent_app_date] => 1994-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 11846
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/465/05465344.pdf
[firstpage_image] =>[orig_patent_app_number] => 352445
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/352445 | Microprocessor with dual-port cache memory for reducing penalty of consecutive memory address accesses | Dec 8, 1994 | Issued |
Array
(
[id] => 3486683
[patent_doc_number] => 05428759
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-27
[patent_title] => 'Associative memory system having segment and page descriptor content-addressable memories'
[patent_app_type] => 1
[patent_app_number] => 8/324864
[patent_app_country] => US
[patent_app_date] => 1994-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 9163
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 390
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/428/05428759.pdf
[firstpage_image] =>[orig_patent_app_number] => 324864
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/324864 | Associative memory system having segment and page descriptor content-addressable memories | Oct 17, 1994 | Issued |
Array
(
[id] => 3430603
[patent_doc_number] => 05434989
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-18
[patent_title] => 'Cache memory for efficient access with address selectors'
[patent_app_type] => 1
[patent_app_number] => 8/323528
[patent_app_country] => US
[patent_app_date] => 1994-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10512
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/434/05434989.pdf
[firstpage_image] =>[orig_patent_app_number] => 323528
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/323528 | Cache memory for efficient access with address selectors | Oct 10, 1994 | Issued |
Array
(
[id] => 3432471
[patent_doc_number] => 05479635
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Memory device including DRAMs for high-speed accessing'
[patent_app_type] => 1
[patent_app_number] => 8/282485
[patent_app_country] => US
[patent_app_date] => 1994-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 8849
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479635.pdf
[firstpage_image] =>[orig_patent_app_number] => 282485
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/282485 | Memory device including DRAMs for high-speed accessing | Jul 31, 1994 | Issued |
Array
(
[id] => 3579444
[patent_doc_number] => 05485589
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-16
[patent_title] => 'Predictive addressing architecture'
[patent_app_type] => 1
[patent_app_number] => 8/278720
[patent_app_country] => US
[patent_app_date] => 1994-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4303
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/485/05485589.pdf
[firstpage_image] =>[orig_patent_app_number] => 278720
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/278720 | Predictive addressing architecture | Jul 21, 1994 | Issued |
Array
(
[id] => 3124662
[patent_doc_number] => 05396451
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-07
[patent_title] => 'DRAM device having cells staggered along adjacent rows and sources and drains aligned in a column direction'
[patent_app_type] => 1
[patent_app_number] => 8/267224
[patent_app_country] => US
[patent_app_date] => 1994-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 5365
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 388
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/396/05396451.pdf
[firstpage_image] =>[orig_patent_app_number] => 267224
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/267224 | DRAM device having cells staggered along adjacent rows and sources and drains aligned in a column direction | Jul 4, 1994 | Issued |
Array
(
[id] => 3549632
[patent_doc_number] => 05481496
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Semiconductor memory device and method of data transfer therefor'
[patent_app_type] => 1
[patent_app_number] => 8/236004
[patent_app_country] => US
[patent_app_date] => 1994-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5377
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 383
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/481/05481496.pdf
[firstpage_image] =>[orig_patent_app_number] => 236004
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/236004 | Semiconductor memory device and method of data transfer therefor | May 1, 1994 | Issued |
Array
(
[id] => 3433373
[patent_doc_number] => 05390312
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-14
[patent_title] => 'Access look-aside facility'
[patent_app_type] => 1
[patent_app_number] => 8/216784
[patent_app_country] => US
[patent_app_date] => 1994-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3899
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 681
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/390/05390312.pdf
[firstpage_image] =>[orig_patent_app_number] => 216784
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/216784 | Access look-aside facility | Mar 22, 1994 | Issued |
Array
(
[id] => 3502769
[patent_doc_number] => 05440717
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Computer pipeline including dual-ported, content-addressable writebuffer'
[patent_app_type] => 1
[patent_app_number] => 8/194136
[patent_app_country] => US
[patent_app_date] => 1994-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2434
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/440/05440717.pdf
[firstpage_image] =>[orig_patent_app_number] => 194136
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/194136 | Computer pipeline including dual-ported, content-addressable writebuffer | Feb 8, 1994 | Issued |
Array
(
[id] => 3430645
[patent_doc_number] => 05390146
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-14
[patent_title] => 'Reference switching circuit for flash EPROM'
[patent_app_type] => 1
[patent_app_number] => 8/192182
[patent_app_country] => US
[patent_app_date] => 1994-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2321
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/390/05390146.pdf
[firstpage_image] =>[orig_patent_app_number] => 192182
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/192182 | Reference switching circuit for flash EPROM | Feb 2, 1994 | Issued |
Array
(
[id] => 3430583
[patent_doc_number] => 05434988
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-18
[patent_title] => 'Data processor implementing a two\'s complement addressing technique'
[patent_app_type] => 1
[patent_app_number] => 8/181692
[patent_app_country] => US
[patent_app_date] => 1994-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2794
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/434/05434988.pdf
[firstpage_image] =>[orig_patent_app_number] => 181692
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/181692 | Data processor implementing a two's complement addressing technique | Jan 13, 1994 | Issued |
08/170609 | PROCESSING DEVICES WITH IMPROVED ADDRESSING CAPABILITIES, SYSTEMS AND METHODS | Dec 20, 1993 | Abandoned |
Array
(
[id] => 3569162
[patent_doc_number] => 05502829
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-26
[patent_title] => 'Apparatus for obtaining data from a translation memory based on carry signal from adder'
[patent_app_type] => 1
[patent_app_number] => 8/148219
[patent_app_country] => US
[patent_app_date] => 1993-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2132
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/502/05502829.pdf
[firstpage_image] =>[orig_patent_app_number] => 148219
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/148219 | Apparatus for obtaining data from a translation memory based on carry signal from adder | Nov 2, 1993 | Issued |
Array
(
[id] => 3122181
[patent_doc_number] => 05408626
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'One clock address pipelining in segmentation unit'
[patent_app_type] => 1
[patent_app_number] => 8/142817
[patent_app_country] => US
[patent_app_date] => 1993-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4173
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/408/05408626.pdf
[firstpage_image] =>[orig_patent_app_number] => 142817
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/142817 | One clock address pipelining in segmentation unit | Oct 25, 1993 | Issued |
Array
(
[id] => 3432365
[patent_doc_number] => 05479628
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Virtual address translation hardware assist circuit and method'
[patent_app_type] => 1
[patent_app_number] => 8/135037
[patent_app_country] => US
[patent_app_date] => 1993-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 6087
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 354
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479628.pdf
[firstpage_image] =>[orig_patent_app_number] => 135037
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/135037 | Virtual address translation hardware assist circuit and method | Oct 11, 1993 | Issued |
Array
(
[id] => 3069266
[patent_doc_number] => 05357621
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-18
[patent_title] => 'Serial architecture for memory module control'
[patent_app_type] => 1
[patent_app_number] => 8/135361
[patent_app_country] => US
[patent_app_date] => 1993-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 8417
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/357/05357621.pdf
[firstpage_image] =>[orig_patent_app_number] => 135361
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/135361 | Serial architecture for memory module control | Oct 11, 1993 | Issued |