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Sunghee Y Gray

Examiner (ID: 4107, Phone: (571)270-3211 , Office: P/2886 )

Most Active Art Unit
2886
Art Unit(s)
2877, 2886
Total Applications
637
Issued Applications
491
Pending Applications
52
Abandoned Applications
94

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1106258 [patent_doc_number] => 06816962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions' [patent_app_type] => B2 [patent_app_number] => 10/082085 [patent_app_country] => US [patent_app_date] => 2002-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3945 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816962.pdf [firstpage_image] =>[orig_patent_app_number] => 10082085 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082085
Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions Feb 24, 2002 Issued
Array ( [id] => 1075166 [patent_doc_number] => 06839834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Microprocessor protected against parasitic interrupt signals' [patent_app_type] => utility [patent_app_number] => 09/826427 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839834.pdf [firstpage_image] =>[orig_patent_app_number] => 09826427 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826427
Microprocessor protected against parasitic interrupt signals Apr 2, 2001 Issued
Array ( [id] => 1112189 [patent_doc_number] => 06810476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Variable state save formats based on operand size of state save instruction' [patent_app_type] => B2 [patent_app_number] => 09/824862 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 14888 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810476.pdf [firstpage_image] =>[orig_patent_app_number] => 09824862 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824862
Variable state save formats based on operand size of state save instruction Apr 1, 2001 Issued
Array ( [id] => 6460588 [patent_doc_number] => 20020178346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Lowering priority and elimination scheme for useless instructions' [patent_app_type] => new [patent_app_number] => 09/822894 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5882 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178346.pdf [firstpage_image] =>[orig_patent_app_number] => 09822894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/822894
System, apparatus and method for prioritizing instructions and eliminating useless instructions Mar 29, 2001 Issued
Array ( [id] => 7626817 [patent_doc_number] => 06807627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Preserving the content of a first register without affecting the content of a second register' [patent_app_type] => B2 [patent_app_number] => 09/765930 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2462 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807627.pdf [firstpage_image] =>[orig_patent_app_number] => 09765930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765930
Preserving the content of a first register without affecting the content of a second register Jan 18, 2001 Issued
Array ( [id] => 1177696 [patent_doc_number] => 06760835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Instruction branch mispredict streaming' [patent_app_type] => B1 [patent_app_number] => 09/721079 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760835.pdf [firstpage_image] =>[orig_patent_app_number] => 09721079 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/721079
Instruction branch mispredict streaming Nov 21, 2000 Issued
Array ( [id] => 1097394 [patent_doc_number] => 06826679 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Processor with pointer tracking to eliminate redundant memory fetches' [patent_app_type] => B1 [patent_app_number] => 09/716493 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9921 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826679.pdf [firstpage_image] =>[orig_patent_app_number] => 09716493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716493
Processor with pointer tracking to eliminate redundant memory fetches Nov 19, 2000 Issued
Array ( [id] => 1052612 [patent_doc_number] => 06862678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'Apparatus and method for data processing using multiply-accumalate instructions' [patent_app_type] => utility [patent_app_number] => 09/709800 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2799 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862678.pdf [firstpage_image] =>[orig_patent_app_number] => 09709800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/709800
Apparatus and method for data processing using multiply-accumalate instructions Nov 8, 2000 Issued
Array ( [id] => 1184822 [patent_doc_number] => 06748522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Performance monitoring based on instruction sampling in a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/703346 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5223 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748522.pdf [firstpage_image] =>[orig_patent_app_number] => 09703346 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/703346
Performance monitoring based on instruction sampling in a microprocessor Oct 30, 2000 Issued
Array ( [id] => 1085043 [patent_doc_number] => 06834338 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-21 [patent_title] => 'Microprocessor with branch-decrement instruction that provides a target and conditionally modifies a test register if the register meets a condition' [patent_app_type] => B1 [patent_app_number] => 09/703144 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 8822 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834338.pdf [firstpage_image] =>[orig_patent_app_number] => 09703144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/703144
Microprocessor with branch-decrement instruction that provides a target and conditionally modifies a test register if the register meets a condition Oct 30, 2000 Issued
Array ( [id] => 1197018 [patent_doc_number] => 06732257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Reducing the length of lower level instructions by splitting and recombining an immediate' [patent_app_type] => B1 [patent_app_number] => 09/675819 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2717 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732257.pdf [firstpage_image] =>[orig_patent_app_number] => 09675819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675819
Reducing the length of lower level instructions by splitting and recombining an immediate Sep 28, 2000 Issued
Array ( [id] => 1092898 [patent_doc_number] => 06829702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Branch target cache and method for efficiently obtaining target path instructions for tight program loops' [patent_app_type] => B1 [patent_app_number] => 09/626247 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4059 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829702.pdf [firstpage_image] =>[orig_patent_app_number] => 09626247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626247
Branch target cache and method for efficiently obtaining target path instructions for tight program loops Jul 25, 2000 Issued
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