Christyann R Pulliam
Supervisory Patent Examiner (ID: 545, Phone: (571)270-1007 , Office: P/2164 )
Most Active Art Unit | 2100 |
Art Unit(s) | 2124, 2164, 2100, 2165 |
Total Applications | 314 |
Issued Applications | 62 |
Pending Applications | 136 |
Abandoned Applications | 115 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5228161
[patent_doc_number] => 20070290268
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-20
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/889099
[patent_app_country] => US
[patent_app_date] => 2007-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9273
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20070290268.pdf
[firstpage_image] =>[orig_patent_app_number] => 11889099
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/889099 | Method of fabricating semiconductor device | Aug 8, 2007 | Abandoned |
Array
(
[id] => 5008090
[patent_doc_number] => 20070278567
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-06
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/882626
[patent_app_country] => US
[patent_app_date] => 2007-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9275
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0278/20070278567.pdf
[firstpage_image] =>[orig_patent_app_number] => 11882626
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/882626 | Method of fabricating semiconductor device | Aug 2, 2007 | Abandoned |
Array
(
[id] => 311021
[patent_doc_number] => 07528045
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'MOS transistor and manufacturing methods thereof'
[patent_app_type] => utility
[patent_app_number] => 11/669164
[patent_app_country] => US
[patent_app_date] => 2007-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 2908
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/528/07528045.pdf
[firstpage_image] =>[orig_patent_app_number] => 11669164
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/669164 | MOS transistor and manufacturing methods thereof | Jan 30, 2007 | Issued |
Array
(
[id] => 557920
[patent_doc_number] => 07470619
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-12-30
[patent_title] => 'Interconnect with high aspect ratio plugged vias'
[patent_app_type] => utility
[patent_app_number] => 11/607494
[patent_app_country] => US
[patent_app_date] => 2006-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5327
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/470/07470619.pdf
[firstpage_image] =>[orig_patent_app_number] => 11607494
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/607494 | Interconnect with high aspect ratio plugged vias | Nov 30, 2006 | Issued |
Array
(
[id] => 4915779
[patent_doc_number] => 20080096379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'FLIP CHIP METALLIZATION METHOD AND DEVICES'
[patent_app_type] => utility
[patent_app_number] => 11/607273
[patent_app_country] => US
[patent_app_date] => 2006-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3856
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20080096379.pdf
[firstpage_image] =>[orig_patent_app_number] => 11607273
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/607273 | Flip chip metallization method and devices | Nov 30, 2006 | Issued |
Array
(
[id] => 795831
[patent_doc_number] => 07429747
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-30
[patent_title] => 'Sb-based CMOS devices'
[patent_app_type] => utility
[patent_app_number] => 11/560494
[patent_app_country] => US
[patent_app_date] => 2006-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 7100
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/429/07429747.pdf
[firstpage_image] =>[orig_patent_app_number] => 11560494
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/560494 | Sb-based CMOS devices | Nov 15, 2006 | Issued |
Array
(
[id] => 5040776
[patent_doc_number] => 20070093058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-26
[patent_title] => 'METHOD FOR PRODUCING ELECTRIC CONTACT AND ELECTRICAL CONNECTOR'
[patent_app_type] => utility
[patent_app_number] => 11/551444
[patent_app_country] => US
[patent_app_date] => 2006-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3412
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20070093058.pdf
[firstpage_image] =>[orig_patent_app_number] => 11551444
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/551444 | METHOD FOR PRODUCING ELECTRIC CONTACT AND ELECTRICAL CONNECTOR | Oct 19, 2006 | Abandoned |
Array
(
[id] => 5193979
[patent_doc_number] => 20070082463
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-12
[patent_title] => 'Semiconductor device with semiconductor chip and adhesive film and method for producing the same'
[patent_app_type] => utility
[patent_app_number] => 11/543983
[patent_app_country] => US
[patent_app_date] => 2006-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3842
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20070082463.pdf
[firstpage_image] =>[orig_patent_app_number] => 11543983
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/543983 | Semiconductor device with semiconductor chip and adhesive film and method for producing the same | Oct 5, 2006 | Issued |
Array
(
[id] => 348802
[patent_doc_number] => 07494918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-24
[patent_title] => 'Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof'
[patent_app_type] => utility
[patent_app_number] => 11/538963
[patent_app_country] => US
[patent_app_date] => 2006-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 24
[patent_no_of_words] => 5776
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/494/07494918.pdf
[firstpage_image] =>[orig_patent_app_number] => 11538963
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/538963 | Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof | Oct 4, 2006 | Issued |
Array
(
[id] => 5177630
[patent_doc_number] => 20070178690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-02
[patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING A METALLIZATION LAYER STACK WITH A POROUS LOW-K MATERIAL HAVING AN ENHANCED INTEGRITY'
[patent_app_type] => utility
[patent_app_number] => 11/538464
[patent_app_country] => US
[patent_app_date] => 2006-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8290
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0178/20070178690.pdf
[firstpage_image] =>[orig_patent_app_number] => 11538464
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/538464 | SEMICONDUCTOR DEVICE COMPRISING A METALLIZATION LAYER STACK WITH A POROUS LOW-K MATERIAL HAVING AN ENHANCED INTEGRITY | Oct 3, 2006 | Abandoned |
Array
(
[id] => 4745790
[patent_doc_number] => 20080090392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'Technique for Improved Damage Control in a Plasma Doping (PLAD) Ion Implantation'
[patent_app_type] => utility
[patent_app_number] => 11/537274
[patent_app_country] => US
[patent_app_date] => 2006-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3027
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20080090392.pdf
[firstpage_image] =>[orig_patent_app_number] => 11537274
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/537274 | Technique for Improved Damage Control in a Plasma Doping (PLAD) Ion Implantation | Sep 28, 2006 | Abandoned |
Array
(
[id] => 5210580
[patent_doc_number] => 20070249164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-25
[patent_title] => 'METHOD OF FABRICATING AN INTERCONNECT STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 11/379384
[patent_app_country] => US
[patent_app_date] => 2006-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2842
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20070249164.pdf
[firstpage_image] =>[orig_patent_app_number] => 11379384
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/379384 | METHOD OF FABRICATING AN INTERCONNECT STRUCTURE | Apr 19, 2006 | Abandoned |
Array
(
[id] => 5832274
[patent_doc_number] => 20060244104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'Trench gate type insulated gate bipolar transistor'
[patent_app_type] => utility
[patent_app_number] => 11/402874
[patent_app_country] => US
[patent_app_date] => 2006-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6180
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0244/20060244104.pdf
[firstpage_image] =>[orig_patent_app_number] => 11402874
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/402874 | Trench gate type insulated gate bipolar transistor | Apr 12, 2006 | Issued |
Array
(
[id] => 5751068
[patent_doc_number] => 20060220217
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'High precision connector member and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/391664
[patent_app_country] => US
[patent_app_date] => 2006-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3723
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0220/20060220217.pdf
[firstpage_image] =>[orig_patent_app_number] => 11391664
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/391664 | High precision connector member and manufacturing method thereof | Mar 27, 2006 | Abandoned |
Array
(
[id] => 887785
[patent_doc_number] => 07348200
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-25
[patent_title] => 'Method of growing non-polar a-plane gallium nitride'
[patent_app_type] => utility
[patent_app_number] => 11/368184
[patent_app_country] => US
[patent_app_date] => 2006-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2965
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/348/07348200.pdf
[firstpage_image] =>[orig_patent_app_number] => 11368184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/368184 | Method of growing non-polar a-plane gallium nitride | Mar 2, 2006 | Issued |
Array
(
[id] => 311042
[patent_doc_number] => 07528066
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'Structure and method for metal integration'
[patent_app_type] => utility
[patent_app_number] => 11/364953
[patent_app_country] => US
[patent_app_date] => 2006-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 6960
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/528/07528066.pdf
[firstpage_image] =>[orig_patent_app_number] => 11364953
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/364953 | Structure and method for metal integration | Feb 28, 2006 | Issued |
Array
(
[id] => 578781
[patent_doc_number] => 07452749
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-18
[patent_title] => 'Method for manufacturing flip-chip type semiconductor device featuring nickel electrode pads, and plating apparatus used in such method'
[patent_app_type] => utility
[patent_app_number] => 11/364274
[patent_app_country] => US
[patent_app_date] => 2006-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 5173
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/452/07452749.pdf
[firstpage_image] =>[orig_patent_app_number] => 11364274
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/364274 | Method for manufacturing flip-chip type semiconductor device featuring nickel electrode pads, and plating apparatus used in such method | Feb 28, 2006 | Issued |
Array
(
[id] => 849110
[patent_doc_number] => 07381628
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-03
[patent_title] => 'Process of making a microtube and microfluidic devices formed therewith'
[patent_app_type] => utility
[patent_app_number] => 11/276233
[patent_app_country] => US
[patent_app_date] => 2006-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3611
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/381/07381628.pdf
[firstpage_image] =>[orig_patent_app_number] => 11276233
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/276233 | Process of making a microtube and microfluidic devices formed therewith | Feb 19, 2006 | Issued |
Array
(
[id] => 5608636
[patent_doc_number] => 20060270152
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TUNGSTEN GATES ELECTRODE'
[patent_app_type] => utility
[patent_app_number] => 11/164804
[patent_app_country] => US
[patent_app_date] => 2005-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3027
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0270/20060270152.pdf
[firstpage_image] =>[orig_patent_app_number] => 11164804
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164804 | Method of manufacturing semiconductor device having tungsten gates electrode | Dec 5, 2005 | Issued |
Array
(
[id] => 813652
[patent_doc_number] => 07413924
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-19
[patent_title] => 'Plasma etch process for defining catalyst pads on nanoemissive displays'
[patent_app_type] => utility
[patent_app_number] => 11/263793
[patent_app_country] => US
[patent_app_date] => 2005-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2594
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/413/07413924.pdf
[firstpage_image] =>[orig_patent_app_number] => 11263793
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/263793 | Plasma etch process for defining catalyst pads on nanoemissive displays | Oct 30, 2005 | Issued |