Search

Justin B Sanders

Examiner (ID: 6293, Phone: (571)272-3894 , Office: P/2422 )

Most Active Art Unit
2422
Art Unit(s)
2422
Total Applications
309
Issued Applications
211
Pending Applications
1
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4130439 [patent_doc_number] => 06146909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Detecting trace levels of copper' [patent_app_type] => 1 [patent_app_number] => 9/197412 [patent_app_country] => US [patent_app_date] => 1998-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2036 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146909.pdf [firstpage_image] =>[orig_patent_app_number] => 197412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/197412
Detecting trace levels of copper Nov 20, 1998 Issued
Array ( [id] => 4245315 [patent_doc_number] => 06136618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor device manufacturing process diagnosis system suitable for diagnoses of manufacturing process of logic LSI composed of a plurality of logic circuit blocks and diagnosis method thereof' [patent_app_type] => 1 [patent_app_number] => 9/197251 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7179 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136618.pdf [firstpage_image] =>[orig_patent_app_number] => 197251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/197251
Semiconductor device manufacturing process diagnosis system suitable for diagnoses of manufacturing process of logic LSI composed of a plurality of logic circuit blocks and diagnosis method thereof Nov 19, 1998 Issued
Array ( [id] => 4130673 [patent_doc_number] => 06121061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method of processing wafers with low mass support' [patent_app_type] => 1 [patent_app_number] => 9/184491 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9621 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121061.pdf [firstpage_image] =>[orig_patent_app_number] => 184491 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/184491
Method of processing wafers with low mass support Nov 1, 1998 Issued
Array ( [id] => 4101055 [patent_doc_number] => 06100101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Sensitive technique for metal-void detection' [patent_app_type] => 1 [patent_app_number] => 9/179172 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3391 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100101.pdf [firstpage_image] =>[orig_patent_app_number] => 179172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179172
Sensitive technique for metal-void detection Oct 26, 1998 Issued
Array ( [id] => 4214702 [patent_doc_number] => 06110800 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method for fabricating a trench isolation' [patent_app_type] => 1 [patent_app_number] => 9/174392 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2370 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110800.pdf [firstpage_image] =>[orig_patent_app_number] => 174392 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174392
Method for fabricating a trench isolation Oct 13, 1998 Issued
Array ( [id] => 4130755 [patent_doc_number] => 06121065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Wafer scale burn-in testing' [patent_app_type] => 1 [patent_app_number] => 9/160751 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4766 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121065.pdf [firstpage_image] =>[orig_patent_app_number] => 160751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160751
Wafer scale burn-in testing Sep 24, 1998 Issued
Array ( [id] => 4236518 [patent_doc_number] => 06090632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method for controlling semiconductor processing equipment in real time' [patent_app_type] => 1 [patent_app_number] => 9/146751 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4277 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090632.pdf [firstpage_image] =>[orig_patent_app_number] => 146751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146751
Method for controlling semiconductor processing equipment in real time Sep 3, 1998 Issued
Array ( [id] => 4070529 [patent_doc_number] => 06069034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'DMOS architecture using low N-source dose co-driven with P-body implant compatible with E.sup.2 PROM core process' [patent_app_type] => 1 [patent_app_number] => 9/146641 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 38 [patent_no_of_words] => 5557 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 465 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069034.pdf [firstpage_image] =>[orig_patent_app_number] => 146641 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146641
DMOS architecture using low N-source dose co-driven with P-body implant compatible with E.sup.2 PROM core process Sep 2, 1998 Issued
Array ( [id] => 4234181 [patent_doc_number] => 06074940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method of making a fuse in a semiconductor device and a semiconductor device having a fuse' [patent_app_type] => 1 [patent_app_number] => 9/122501 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2523 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074940.pdf [firstpage_image] =>[orig_patent_app_number] => 122501 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122501
Method of making a fuse in a semiconductor device and a semiconductor device having a fuse Jul 23, 1998 Issued
Array ( [id] => 3934537 [patent_doc_number] => 05972727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Reticle sorter' [patent_app_type] => 1 [patent_app_number] => 9/107111 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972727.pdf [firstpage_image] =>[orig_patent_app_number] => 107111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107111
Reticle sorter Jun 29, 1998 Issued
Array ( [id] => 3934524 [patent_doc_number] => 05972726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method of detecting concentration of contamination on a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/098872 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3077 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972726.pdf [firstpage_image] =>[orig_patent_app_number] => 098872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098872
Method of detecting concentration of contamination on a semiconductor wafer Jun 16, 1998 Issued
Array ( [id] => 3944572 [patent_doc_number] => 05998290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method to protect gate stack material during source/drain reoxidation' [patent_app_type] => 1 [patent_app_number] => 9/097353 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2658 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998290.pdf [firstpage_image] =>[orig_patent_app_number] => 097353 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097353
Method to protect gate stack material during source/drain reoxidation Jun 14, 1998 Issued
09/090563 METHOD AND APPARATUS FOR PREVENTING CHIP BREAKAGE DURING SEMICONDUCTOR MANUFACTURING USING WAFER GRINDING STRIATION INFORMATION Jun 3, 1998 Issued
Array ( [id] => 4139897 [patent_doc_number] => 06060406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'MOS transistors with improved gate dielectrics' [patent_app_type] => 1 [patent_app_number] => 9/086252 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3896 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060406.pdf [firstpage_image] =>[orig_patent_app_number] => 086252 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086252
MOS transistors with improved gate dielectrics May 27, 1998 Issued
09/085490 METHOD FOR FABRICATING CAPACITORS OF A DYNAMIC RANDOM ACCESS MEMORY May 26, 1998 Issued
Array ( [id] => 4185934 [patent_doc_number] => 06093627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Self-aligned contact process using silicon spacers' [patent_app_type] => 1 [patent_app_number] => 9/075790 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1805 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093627.pdf [firstpage_image] =>[orig_patent_app_number] => 075790 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075790
Self-aligned contact process using silicon spacers May 11, 1998 Issued
Array ( [id] => 4214107 [patent_doc_number] => 06110759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Composite structure with a growth substrate having a diamond layer and a plurality of microelectronic components, and process for producing such a composite structure' [patent_app_type] => 1 [patent_app_number] => 9/070853 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3968 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110759.pdf [firstpage_image] =>[orig_patent_app_number] => 070853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070853
Composite structure with a growth substrate having a diamond layer and a plurality of microelectronic components, and process for producing such a composite structure Apr 30, 1998 Issued
Array ( [id] => 4124417 [patent_doc_number] => 06127196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method for testing a tape carrier package' [patent_app_type] => 1 [patent_app_number] => 9/069273 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2710 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127196.pdf [firstpage_image] =>[orig_patent_app_number] => 069273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069273
Method for testing a tape carrier package Apr 28, 1998 Issued
Array ( [id] => 4190920 [patent_doc_number] => 06130104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Cleaner for inspecting projections, and inspection apparatus and method for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/055291 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130104.pdf [firstpage_image] =>[orig_patent_app_number] => 055291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055291
Cleaner for inspecting projections, and inspection apparatus and method for integrated circuits Apr 5, 1998 Issued
Array ( [id] => 4095252 [patent_doc_number] => 06096645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method of making IC devices having stable CVD titanium nitride films' [patent_app_type] => 1 [patent_app_number] => 9/034863 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2847 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096645.pdf [firstpage_image] =>[orig_patent_app_number] => 034863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034863
Method of making IC devices having stable CVD titanium nitride films Mar 3, 1998 Issued
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