Search

Michael S Leslie

Examiner (ID: 6992, Phone: (571)272-4819 , Office: P/3745 )

Most Active Art Unit
3745
Art Unit(s)
3745
Total Applications
2382
Issued Applications
1969
Pending Applications
85
Abandoned Applications
328

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17993461 [patent_doc_number] => 20220359498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/870847 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870847 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870847
Three-dimensional integrated circuit structures and method of forming the same Jul 21, 2022 Issued
Array ( [id] => 17870938 [patent_doc_number] => 20220293675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => MONOLITHIC SEGMENTED LED ARRAY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/832460 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832460 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832460
Monolithic segmented LED array architecture Jun 2, 2022 Issued
Array ( [id] => 17708956 [patent_doc_number] => 20220208964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/655336 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/655336
Power device integration on a common substrate Mar 16, 2022 Issued
Array ( [id] => 18645691 [patent_doc_number] => 11769771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => FinFET device having flat-top epitaxial features and method of making the same [patent_app_type] => utility [patent_app_number] => 17/694108 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 6484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694108 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694108
FinFET device having flat-top epitaxial features and method of making the same Mar 13, 2022 Issued
Array ( [id] => 18008670 [patent_doc_number] => 20220367437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Semiconductor capacitor array layout with dummy capacitor structure [patent_app_type] => utility [patent_app_number] => 17/677256 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17677256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/677256
Semiconductor capacitor array layout with dummy capacitor structure Feb 21, 2022 Issued
Array ( [id] => 18379924 [patent_doc_number] => 20230155013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/529863 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529863 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529863
SEMICONDUCTOR DEVICE Nov 17, 2021 Abandoned
Array ( [id] => 18336365 [patent_doc_number] => 20230128314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => VERTICAL FIELD EFFECT TRANSISTOR WITH DUAL THRESHOLD VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/452341 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452341 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452341
Vertical field effect transistor with dual threshold voltage Oct 25, 2021 Issued
Array ( [id] => 17403080 [patent_doc_number] => 20220045171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/497700 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/497700
Semiconductor device having two-dimensional MOSFET Oct 7, 2021 Issued
Array ( [id] => 18097537 [patent_doc_number] => 20220415878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => ELECTROSTATIC DISCHARGE PREVENTION [patent_app_type] => utility [patent_app_number] => 17/495638 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495638
Electrostatic discharge prevention Oct 5, 2021 Issued
Array ( [id] => 18937221 [patent_doc_number] => 11889686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Vertical memory devices [patent_app_type] => utility [patent_app_number] => 17/468596 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6340 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468596
Vertical memory devices Sep 6, 2021 Issued
Array ( [id] => 17303160 [patent_doc_number] => 20210398999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/462736 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462736
Method of fabrication thereof a multi-level vertical memory device including inter-level channel connector Aug 30, 2021 Issued
Array ( [id] => 17232681 [patent_doc_number] => 20210359238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => QUANTUM DOT DEVICE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/387281 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387281
Quantum dot device and display device Jul 27, 2021 Issued
Array ( [id] => 17115720 [patent_doc_number] => 20210296317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => METHOD OF FORMING HIGH PERFORMANCE MOSFETS HAVING VARYING CHANNEL STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/340217 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340217
High performance MOSFETs having varying channel structures Jun 6, 2021 Issued
Array ( [id] => 17247367 [patent_doc_number] => 20210367112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => WAFER LEVEL PACKAGING OF MULTIPLE LIGHT EMITTING DIODES (LEDS) ON A SINGLE CARRIER DIE [patent_app_type] => utility [patent_app_number] => 17/325970 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325970
WAFER LEVEL PACKAGING OF MULTIPLE LIGHT EMITTING DIODES (LEDS) ON A SINGLE CARRIER DIE May 19, 2021 Abandoned
Array ( [id] => 17536913 [patent_doc_number] => 20220115522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/242587 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242587 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242587
Semiconductor device comprising a buffer layer including a complex defect of interstice carbon and interstice oxygen Apr 27, 2021 Issued
Array ( [id] => 18520839 [patent_doc_number] => 11710734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Cascode-connected JFET-MOSFET semiconductor device [patent_app_type] => utility [patent_app_number] => 17/212621 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6237 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212621
Cascode-connected JFET-MOSFET semiconductor device Mar 24, 2021 Issued
Array ( [id] => 18967571 [patent_doc_number] => 11901353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Integrated circuits including coil circuit and SCR [patent_app_type] => utility [patent_app_number] => 17/200527 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200527 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200527
Integrated circuits including coil circuit and SCR Mar 11, 2021 Issued
Array ( [id] => 17277991 [patent_doc_number] => 20210384189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/198170 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198170 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198170
Semiconductor device Mar 9, 2021 Issued
Array ( [id] => 17130645 [patent_doc_number] => 20210305414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => POWER DEVICE HAVING LATERAL INSULATED GATE BIPOLAR TRANSISTOR (LIGBT) AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/187540 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187540
Power device having lateral insulated gate bipolar transistor (LIGBT) and manufacturing method thereof Feb 25, 2021 Issued
Array ( [id] => 18797035 [patent_doc_number] => 11830870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => ESD protection device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/185722 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7310 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185722
ESD protection device and manufacturing method thereof Feb 24, 2021 Issued
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