Joseph D Torres

Array ( [id] => 1595840 [patent_doc_number] => 06484228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method and apparatus for data compression and decompression for a data processor system' [patent_app_type] => B2 [patent_app_number] => 10/008074 [patent_app_country] => US [patent_app_date] => 2001-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5009 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484228.pdf [firstpage_image] =>[orig_patent_app_number] => 10008074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1409591 [patent_doc_number] => 06557091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Data processor with localized memory reclamation' [patent_app_type] => B2 [patent_app_number] => 09/866819 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4642 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557091.pdf [firstpage_image] =>[orig_patent_app_number] => 09866819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6986283 [patent_doc_number] => 20010036115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Logic partitioning of a nonvolatile memory array' [patent_app_type] => new [patent_app_number] => 09/817804 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3760 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036115.pdf [firstpage_image] =>[orig_patent_app_number] => 09817804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6560978 [patent_doc_number] => 20020138690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'System and method for performing a partial DRAM refresh' [patent_app_type] => new [patent_app_number] => 09/815516 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3081 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138690.pdf [firstpage_image] =>[orig_patent_app_number] => 09815516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431092 [patent_doc_number] => 06507901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Allocating storage for aligned data' [patent_app_type] => B1 [patent_app_number] => 09/816283 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 9783 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507901.pdf [firstpage_image] =>[orig_patent_app_number] => 09816283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1423580 [patent_doc_number] => 06539464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Memory allocator for multithread environment' [patent_app_type] => B1 [patent_app_number] => 09/816280 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 10873 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 514 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539464.pdf [firstpage_image] =>[orig_patent_app_number] => 09816280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7638612 [patent_doc_number] => 06397309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-28 [patent_title] => 'System and method for reconstructing data associated with protected storage volume stored in multiple modules of back-up mass data storage facility' [patent_app_type] => B2 [patent_app_number] => 09/803770 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 23285 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397309.pdf [firstpage_image] =>[orig_patent_app_number] => 09803770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1406893 [patent_doc_number] => 06560690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'System and method for employing a global bit for page sharing in a linear-addressed cache' [patent_app_type] => B2 [patent_app_number] => 09/753330 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5401 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560690.pdf [firstpage_image] =>[orig_patent_app_number] => 09753330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1298060 [patent_doc_number] => 06631446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Self-tuning buffer management' [patent_app_type] => B1 [patent_app_number] => 09/696883 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5391 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631446.pdf [firstpage_image] =>[orig_patent_app_number] => 09696883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587406 [patent_doc_number] => 06425054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Multiprocessor operation in a multimedia signal processor' [patent_app_type] => B1 [patent_app_number] => 09/685982 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6854 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425054.pdf [firstpage_image] =>[orig_patent_app_number] => 09685982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1497851 [patent_doc_number] => 06343354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Method and apparatus for compression, decompression, and execution of program code' [patent_app_type] => B1 [patent_app_number] => 09/552304 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4996 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343354.pdf [firstpage_image] =>[orig_patent_app_number] => 09552304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4412368 [patent_doc_number] => 06298424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation' [patent_app_type] => 1 [patent_app_number] => 9/522649 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6591 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298424.pdf [firstpage_image] =>[orig_patent_app_number] => 522649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1308803 [patent_doc_number] => 06629209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Cache coherency protocol permitting sharing of a locked data granule' [patent_app_type] => B1 [patent_app_number] => 09/437185 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629209.pdf [firstpage_image] =>[orig_patent_app_number] => 09437185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1308835 [patent_doc_number] => 06629212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'High speed lock acquisition mechanism with time parameterized cache coherency states' [patent_app_type] => B1 [patent_app_number] => 09/437187 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4374 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629212.pdf [firstpage_image] =>[orig_patent_app_number] => 09437187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1415759 [patent_doc_number] => 06549989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Extended cache coherency protocol with a lock released state' [patent_app_type] => B1 [patent_app_number] => 09/437184 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4398 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549989.pdf [firstpage_image] =>[orig_patent_app_number] => 09437184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416948 [patent_doc_number] => 06532523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Apparatus for processing memory access requests' [patent_app_type] => B1 [patent_app_number] => 09/417272 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3926 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532523.pdf [firstpage_image] =>[orig_patent_app_number] => 09417272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1584726 [patent_doc_number] => 06449682 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'System and method for inserting one or more files onto mass storage' [patent_app_type] => B1 [patent_app_number] => 09/336281 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6974 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449682.pdf [firstpage_image] =>[orig_patent_app_number] => 09336281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7642397 [patent_doc_number] => 06430649 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method and apparatus for enforcing memory reference dependencies through a load store unit' [patent_app_type] => B1 [patent_app_number] => 09/327398 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6681 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430649.pdf [firstpage_image] =>[orig_patent_app_number] => 09327398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1365315 [patent_doc_number] => 06581141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Toggle for split transaction mode of PCI-X bridge buffer' [patent_app_type] => B1 [patent_app_number] => 09/314045 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3153 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581141.pdf [firstpage_image] =>[orig_patent_app_number] => 09314045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1339148 [patent_doc_number] => 06601134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Multi-processor type storage control apparatus for performing access control through selector' [patent_app_type] => B1 [patent_app_number] => 09/298967 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 13144 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601134.pdf [firstpage_image] =>[orig_patent_app_number] => 09298967 [rel_patent_id] =>[rel_patent_doc_number] =>)