Search

Theodore E Hebert

Examiner (ID: 8656, Phone: (571)270-1409 , Office: P/2199 )

Most Active Art Unit
2199
Art Unit(s)
2199, 2198
Total Applications
490
Issued Applications
341
Pending Applications
61
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16250158 [patent_doc_number] => 10749541 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-18 [patent_title] => Time interleaved analog to digital converter with digital equalization and a reduced number of multipliers [patent_app_type] => utility [patent_app_number] => 16/736352 [patent_app_country] => US [patent_app_date] => 2020-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4158 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736352
Time interleaved analog to digital converter with digital equalization and a reduced number of multipliers Jan 6, 2020 Issued
Array ( [id] => 16496446 [patent_doc_number] => 10862503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator [patent_app_type] => utility [patent_app_number] => 16/702246 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4870 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702246
Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator Dec 2, 2019 Issued
Array ( [id] => 15940905 [patent_doc_number] => 20200162086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => PIPELINED-INTERPOLATING ANALOG-TO-DIGITAL CONVERTER [patent_app_type] => utility [patent_app_number] => 16/684263 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684263 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684263
Pipelined-interpolating analog-to-digital converter Nov 13, 2019 Issued
Array ( [id] => 15626945 [patent_doc_number] => 20200083877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => CURRENT STEERING CIRCUIT, CORRESPONDING DEVICE, SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 16/680831 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680831 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680831
Current steering circuit, corresponding device, system and method Nov 11, 2019 Issued
Array ( [id] => 16333181 [patent_doc_number] => 20200304147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => METHOD AND APPARATUS FOR VARIABLE RATE COMPRESSION WITH A CONDITIONAL AUTOENCODER [patent_app_type] => utility [patent_app_number] => 16/576166 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/576166
Method and apparatus for variable rate compression with a conditional autoencoder Sep 18, 2019 Issued
Array ( [id] => 16265307 [patent_doc_number] => 10756758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-25 [patent_title] => Length-limited huffman encoding [patent_app_type] => utility [patent_app_number] => 16/556925 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556925 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556925
Length-limited huffman encoding Aug 29, 2019 Issued
Array ( [id] => 16247244 [patent_doc_number] => 10746594 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-18 [patent_title] => Thermopile bias method for low voltage infrared readout integrated circuits [patent_app_type] => utility [patent_app_number] => 16/532062 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16532062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/532062
Thermopile bias method for low voltage infrared readout integrated circuits Aug 4, 2019 Issued
Array ( [id] => 15353009 [patent_doc_number] => 20200014396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with Overlapping Reference Voltage Ranges [patent_app_type] => utility [patent_app_number] => 16/532374 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16532374 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/532374
Successive approximation register (SAR) analog to digital converter (ADC) with overlapping reference voltage ranges Aug 4, 2019 Issued
Array ( [id] => 16418602 [patent_doc_number] => 10826512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-03 [patent_title] => System and method for removing error in a system having an analog-to-digital converter [patent_app_type] => utility [patent_app_number] => 16/530618 [patent_app_country] => US [patent_app_date] => 2019-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6165 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16530618 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/530618
System and method for removing error in a system having an analog-to-digital converter Aug 1, 2019 Issued
Array ( [id] => 15124735 [patent_doc_number] => 20190349001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => COMPRESSION AND DECOMPRESSION ENGINES AND COMPRESSED DOMAIN PROCESSORS [patent_app_type] => utility [patent_app_number] => 16/518602 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518602 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518602
Compression and decompression engines and compressed domain processors Jul 21, 2019 Issued
Array ( [id] => 16173586 [patent_doc_number] => 10715172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-14 [patent_title] => Analog-to-digital converter with adjustable operation frequency for noise reduction [patent_app_type] => utility [patent_app_number] => 16/460516 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3775 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16460516 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/460516
Analog-to-digital converter with adjustable operation frequency for noise reduction Jul 1, 2019 Issued
Array ( [id] => 15333653 [patent_doc_number] => 20200007156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Guaranteed Data Compression [patent_app_type] => utility [patent_app_number] => 16/456885 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456885 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/456885
Guaranteed data compression Jun 27, 2019 Issued
Array ( [id] => 15333643 [patent_doc_number] => 20200007151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Guaranteed Data Compression [patent_app_type] => utility [patent_app_number] => 16/457148 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457148
Guaranteed data compression Jun 27, 2019 Issued
Array ( [id] => 15333635 [patent_doc_number] => 20200007147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Use of Differently Delayed Feedback to Suppress Metastability in Noise Shaping Control Loops [patent_app_type] => utility [patent_app_number] => 16/454812 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16454812 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/454812
Use of differently delayed feedback to suppress metastability in noise shaping control loops Jun 26, 2019 Issued
Array ( [id] => 15793157 [patent_doc_number] => 10630314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-21 [patent_title] => Method and system for asynchronous serialization of multiple serial communication signals [patent_app_type] => utility [patent_app_number] => 16/444198 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 15 [patent_no_of_words] => 10040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444198
Method and system for asynchronous serialization of multiple serial communication signals Jun 17, 2019 Issued
Array ( [id] => 15734753 [patent_doc_number] => 10615818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-07 [patent_title] => Mixed chopping and correlated double sampling two-step analog-to-digital converter [patent_app_type] => utility [patent_app_number] => 16/429053 [patent_app_country] => US [patent_app_date] => 2019-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4143 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/429053
Mixed chopping and correlated double sampling two-step analog-to-digital converter Jun 1, 2019 Issued
Array ( [id] => 16339873 [patent_doc_number] => 10790845 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-29 [patent_title] => Clocking circuit and method for time-interleaved analog-to-digital converters [patent_app_type] => utility [patent_app_number] => 16/427922 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/427922
Clocking circuit and method for time-interleaved analog-to-digital converters May 30, 2019 Issued
Array ( [id] => 15734745 [patent_doc_number] => 10615814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-07 [patent_title] => Pipelined analog-to-digital converter [patent_app_type] => utility [patent_app_number] => 16/428282 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3373 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16428282 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/428282
Pipelined analog-to-digital converter May 30, 2019 Issued
Array ( [id] => 14788259 [patent_doc_number] => 20190269027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => HIGH TOLERANCE CONNECTION BETWEEN ELEMENTS [patent_app_type] => utility [patent_app_number] => 16/412078 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412078
High tolerance connection between elements May 13, 2019 Issued
Array ( [id] => 15952521 [patent_doc_number] => 10664165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-26 [patent_title] => Managing inline data compression and deduplication in storage systems [patent_app_type] => utility [patent_app_number] => 16/409366 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16409366 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/409366
Managing inline data compression and deduplication in storage systems May 9, 2019 Issued
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