David S Blum

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Array ( [id] => 18320315 [patent_doc_number] => 20230118443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => Profiling User Activity To Achieve Social And Governance Objectives [patent_app_type] => utility [patent_app_number] => 17/936992 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18727600 [patent_doc_number] => 20230341891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => GLITCH-FREE CLOCK SWITCHING CIRCUIT WITH CLOCK LOSS TOLERANCE AND OPERATION METHOD THEREOF AND GLITCH-FREE CLOCK SWITCHING DEVICE [patent_app_type] => utility [patent_app_number] => 17/896084 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18819304 [patent_doc_number] => 20230393644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => VOLTAGE FREQUENCY SCALING BASED ON ERROR RATE [patent_app_type] => utility [patent_app_number] => 17/893850 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893850 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 18925554 [patent_doc_number] => 20240028558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => DISABLING PROCESSOR CORES FOR BEST LATENCY IN A MULTIPLE CORE PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/871034 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871034 [rel_patent_id] =>[rel_patent_doc_number] =>)

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