Search

Alain L Bashore

Examiner (ID: 8907)

Most Active Art Unit
1762
Art Unit(s)
1762, 3624, 1792
Total Applications
396
Issued Applications
224
Pending Applications
40
Abandoned Applications
128

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17331481 [patent_doc_number] => 11221945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/742872 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5347 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16742872 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/742872
Semiconductor memory device Jan 13, 2020 Issued
Array ( [id] => 15870751 [patent_doc_number] => 20200142779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => EFFICIENT MANAGEMENT OF POINT IN TIME COPIES OF DATA IN OBJECT STORAGE [patent_app_type] => utility [patent_app_number] => 16/735513 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735513 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735513
Efficient management of point in time copies of data in object storage by sending the point in time copies, and a directive for manipulating the point in time copies, to the object storage Jan 5, 2020 Issued
Array ( [id] => 15870861 [patent_doc_number] => 20200142834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => WAIT CLASSIFIED CACHE WRITES IN A DATA STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/732890 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732890 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732890
Wait classified cache writes in a data storage system Jan 1, 2020 Issued
Array ( [id] => 16345992 [patent_doc_number] => 20200310643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD AND COMPUTER PROGRAM PRODUCT FOR READING PARTIAL DATA OF A PAGE ON MULTIPLE PLANES [patent_app_type] => utility [patent_app_number] => 16/730159 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730159 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730159
Method and computer program product for reading partial data of a page on multiple planes Dec 29, 2019 Issued
Array ( [id] => 17415872 [patent_doc_number] => 20220050776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => CONTENT-ADDRESSABLE MEMORY FOR SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/415673 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17415673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/415673
Content-addressable memory for signal development caching in a memory device Dec 19, 2019 Issued
Array ( [id] => 17621779 [patent_doc_number] => 11340833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Systems and methods for data relocation using a signal development cache [patent_app_type] => utility [patent_app_number] => 16/722981 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 46684 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/722981
Systems and methods for data relocation using a signal development cache Dec 19, 2019 Issued
Array ( [id] => 17729609 [patent_doc_number] => 11385997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Controller for managing super block, memory system having the same, and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/690643 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8027 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16690643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/690643
Controller for managing super block, memory system having the same, and operating method thereof Nov 20, 2019 Issued
Array ( [id] => 17238229 [patent_doc_number] => 11182107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Selective allocation of redundant data blocks to background operations [patent_app_type] => utility [patent_app_number] => 16/683968 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 19556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683968
Selective allocation of redundant data blocks to background operations Nov 13, 2019 Issued
Array ( [id] => 18189645 [patent_doc_number] => 11580233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-14 [patent_title] => Baseboard-management-controller storage module [patent_app_type] => utility [patent_app_number] => 16/682943 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682943 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682943
Baseboard-management-controller storage module Nov 12, 2019 Issued
Array ( [id] => 17423161 [patent_doc_number] => 11256615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Apparatus and method for managing map segment using map miss ratio of memory in a memory system [patent_app_type] => utility [patent_app_number] => 16/681076 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10967 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681076 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681076
Apparatus and method for managing map segment using map miss ratio of memory in a memory system Nov 11, 2019 Issued
Array ( [id] => 17729634 [patent_doc_number] => 11386024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Memory module having an open-drain output for parity error and for training sequences [patent_app_type] => utility [patent_app_number] => 16/680060 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 8251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680060 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680060
Memory module having an open-drain output for parity error and for training sequences Nov 10, 2019 Issued
Array ( [id] => 17288323 [patent_doc_number] => 11204873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Pre-decompressing a compressed form of data that has been pre-fetched into a cache to facilitate subsequent retrieval of a decompressed form of the data from the cache [patent_app_type] => utility [patent_app_number] => 16/678826 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16678826 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/678826
Pre-decompressing a compressed form of data that has been pre-fetched into a cache to facilitate subsequent retrieval of a decompressed form of the data from the cache Nov 7, 2019 Issued
Array ( [id] => 15500345 [patent_doc_number] => 20200050361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => Dynamic Access in Flash System [patent_app_type] => utility [patent_app_number] => 16/655792 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655792 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655792
Dynamic access in flash system Oct 16, 2019 Issued
Array ( [id] => 17757397 [patent_doc_number] => 11397689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Memory manager having an address translation function, data processing structure including the same, and method for generating address translation information [patent_app_type] => utility [patent_app_number] => 16/596104 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8021 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596104
Memory manager having an address translation function, data processing structure including the same, and method for generating address translation information Oct 7, 2019 Issued
Array ( [id] => 16346332 [patent_doc_number] => 20200310983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => CONTROLLER, MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/595013 [patent_app_country] => US [patent_app_date] => 2019-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16595013 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/595013
Controller, memory system and operating method thereof for controlling a non-volatile memory device during a sync-up operation Oct 6, 2019 Issued
Array ( [id] => 16751382 [patent_doc_number] => 20210103391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => RESTRICTING WRITE CYCLES TO EXTEND THE LIFETIME OF NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/592196 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/592196
Restricting write cycles to extend the lifetime of nonvolatile memory Oct 2, 2019 Issued
Array ( [id] => 15440217 [patent_doc_number] => 20200034292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => ADAPTABLE DATA CACHING MECHANISM FOR IN-MEMORY CLUSTER COMPUTING [patent_app_type] => utility [patent_app_number] => 16/591612 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/591612
ADAPTABLE DATA CACHING MECHANISM FOR IN-MEMORY CLUSTER COMPUTING Oct 1, 2019 Pending
Array ( [id] => 15349409 [patent_doc_number] => 20200012596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => MANAGING BLOCK ARRANGEMENT OF SUPER BLOCKS [patent_app_type] => utility [patent_app_number] => 16/572922 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/572922
Managing block arrangement of super blocks Sep 16, 2019 Issued
Array ( [id] => 15328727 [patent_doc_number] => 20200004693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => STORAGE SYSTEM AND METHOD FOR PERFORMING AND AUTHENTICATING WRITE-PROTECTION THEREOF [patent_app_type] => utility [patent_app_number] => 16/567355 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567355 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567355
Storage system and method for performing and authenticating write-protection thereof Sep 10, 2019 Issued
Array ( [id] => 15714583 [patent_doc_number] => 20200104058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => SECONDARY STORAGE OPERATION INSTRUCTION TAGS IN INFORMATION MANAGEMENT SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/566322 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566322
SECONDARY STORAGE OPERATION INSTRUCTION TAGS IN INFORMATION MANAGEMENT SYSTEMS Sep 9, 2019 Abandoned
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