Bao Thuy L Nguyen
Examiner (ID: 2543)
Most Active Art Unit | 1641 |
Art Unit(s) | 1641, 1677, 1802 |
Total Applications | 986 |
Issued Applications | 447 |
Pending Applications | 220 |
Abandoned Applications | 283 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3592003
[patent_doc_number] => 05552722
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Mask registor for a configurable cellular array'
[patent_app_type] => 1
[patent_app_number] => 8/486464
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 61
[patent_no_of_words] => 27754
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/552/05552722.pdf
[firstpage_image] =>[orig_patent_app_number] => 486464
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/486464 | Mask registor for a configurable cellular array | Jun 6, 1995 | Issued |
Array
(
[id] => 3625994
[patent_doc_number] => 05614848
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'High-speed semiconductor integrated circuit device composed of CMOS and bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 8/482570
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 56
[patent_figures_cnt] => 80
[patent_no_of_words] => 33654
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 366
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/614/05614848.pdf
[firstpage_image] =>[orig_patent_app_number] => 482570
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/482570 | High-speed semiconductor integrated circuit device composed of CMOS and bipolar transistors | Jun 6, 1995 | Issued |
Array
(
[id] => 3530700
[patent_doc_number] => 05528176
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Register with duplicate decoders for configurable cellular array'
[patent_app_type] => 1
[patent_app_number] => 8/486460
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 61
[patent_no_of_words] => 27745
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/528/05528176.pdf
[firstpage_image] =>[orig_patent_app_number] => 486460
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/486460 | Register with duplicate decoders for configurable cellular array | Jun 6, 1995 | Issued |
Array
(
[id] => 4418154
[patent_doc_number] => 06301065
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-09
[patent_title] => 'Method for recording and reproducing CRT various types of data so as to permit the use of the same mechanical and servo systems thereof'
[patent_app_type] => 1
[patent_app_number] => 8/480934
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 26
[patent_no_of_words] => 6495
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 295
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/301/06301065.pdf
[firstpage_image] =>[orig_patent_app_number] => 480934
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/480934 | Method for recording and reproducing CRT various types of data so as to permit the use of the same mechanical and servo systems thereof | Jun 6, 1995 | Issued |
Array
(
[id] => 3561786
[patent_doc_number] => 05500609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-19
[patent_title] => 'Wildcard addressing structure for configurable cellular array'
[patent_app_type] => 1
[patent_app_number] => 8/486175
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 61
[patent_no_of_words] => 27743
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/500/05500609.pdf
[firstpage_image] =>[orig_patent_app_number] => 486175
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/486175 | Wildcard addressing structure for configurable cellular array | Jun 5, 1995 | Issued |
Array
(
[id] => 3530553
[patent_doc_number] => 05528165
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Logic signal validity verification apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/458001
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2354
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/528/05528165.pdf
[firstpage_image] =>[orig_patent_app_number] => 458001
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/458001 | Logic signal validity verification apparatus | May 31, 1995 | Issued |
Array
(
[id] => 3558881
[patent_doc_number] => 05574391
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'ECL integrated circuit allowing fast operation'
[patent_app_type] => 1
[patent_app_number] => 8/453120
[patent_app_country] => US
[patent_app_date] => 1995-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 5060
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/574/05574391.pdf
[firstpage_image] =>[orig_patent_app_number] => 453120
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/453120 | ECL integrated circuit allowing fast operation | May 29, 1995 | Issued |
Array
(
[id] => 3535680
[patent_doc_number] => 05583453
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Incrementor/decrementor'
[patent_app_type] => 1
[patent_app_number] => 8/451214
[patent_app_country] => US
[patent_app_date] => 1995-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1922
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 543
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583453.pdf
[firstpage_image] =>[orig_patent_app_number] => 451214
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/451214 | Incrementor/decrementor | May 25, 1995 | Issued |
Array
(
[id] => 3669941
[patent_doc_number] => 05598112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Circuit for generating a demand-based gated clock'
[patent_app_type] => 1
[patent_app_number] => 8/451219
[patent_app_country] => US
[patent_app_date] => 1995-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2309
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 340
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/598/05598112.pdf
[firstpage_image] =>[orig_patent_app_number] => 451219
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/451219 | Circuit for generating a demand-based gated clock | May 25, 1995 | Issued |
Array
(
[id] => 3628689
[patent_doc_number] => 05612633
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-18
[patent_title] => 'Circuit for simultaneously inputting and outputting signals on a single wire'
[patent_app_type] => 1
[patent_app_number] => 8/450714
[patent_app_country] => US
[patent_app_date] => 1995-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 7418
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/612/05612633.pdf
[firstpage_image] =>[orig_patent_app_number] => 450714
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/450714 | Circuit for simultaneously inputting and outputting signals on a single wire | May 24, 1995 | Issued |
Array
(
[id] => 3499897
[patent_doc_number] => 05508634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-16
[patent_title] => 'Semiconductor integrated circuit device of dual configuration having enhanced soft error withstanding capacity'
[patent_app_type] => 1
[patent_app_number] => 8/448875
[patent_app_country] => US
[patent_app_date] => 1995-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 5391
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/508/05508634.pdf
[firstpage_image] =>[orig_patent_app_number] => 448875
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/448875 | Semiconductor integrated circuit device of dual configuration having enhanced soft error withstanding capacity | May 23, 1995 | Issued |
Array
(
[id] => 3532183
[patent_doc_number] => 05541536
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Rubberband logic'
[patent_app_type] => 1
[patent_app_number] => 8/448886
[patent_app_country] => US
[patent_app_date] => 1995-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 9802
[patent_no_of_claims] => 22
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[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541536.pdf
[firstpage_image] =>[orig_patent_app_number] => 448886
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/448886 | Rubberband logic | May 23, 1995 | Issued |
Array
(
[id] => 3669844
[patent_doc_number] => 05598106
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Semiconductor integrated circuit for preventing deterioration of the characteristics of an N-channel type transistor'
[patent_app_type] => 1
[patent_app_number] => 8/445412
[patent_app_country] => US
[patent_app_date] => 1995-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3561
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/598/05598106.pdf
[firstpage_image] =>[orig_patent_app_number] => 445412
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/445412 | Semiconductor integrated circuit for preventing deterioration of the characteristics of an N-channel type transistor | May 18, 1995 | Issued |
Array
(
[id] => 3584861
[patent_doc_number] => 05491433
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'Cascode array cell partitioning for a sense amplifier of a programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/444306
[patent_app_country] => US
[patent_app_date] => 1995-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3031
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/491/05491433.pdf
[firstpage_image] =>[orig_patent_app_number] => 444306
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/444306 | Cascode array cell partitioning for a sense amplifier of a programmable logic device | May 17, 1995 | Issued |
Array
(
[id] => 3639728
[patent_doc_number] => 05610534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Logic module for a programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/505830
[patent_app_country] => US
[patent_app_date] => 1995-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/610/05610534.pdf
[firstpage_image] =>[orig_patent_app_number] => 505830
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/505830 | Logic module for a programmable logic device | May 17, 1995 | Issued |
Array
(
[id] => 3560473
[patent_doc_number] => 05543730
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Techniques for programming programmable logic array devices'
[patent_app_type] => 1
[patent_app_number] => 8/442801
[patent_app_country] => US
[patent_app_date] => 1995-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/543/05543730.pdf
[firstpage_image] =>[orig_patent_app_number] => 442801
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/442801 | Techniques for programming programmable logic array devices | May 16, 1995 | Issued |
Array
(
[id] => 3532090
[patent_doc_number] => 05541530
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks'
[patent_app_type] => 1
[patent_app_number] => 8/442802
[patent_app_country] => US
[patent_app_date] => 1995-05-17
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541530.pdf
[firstpage_image] =>[orig_patent_app_number] => 442802
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/442802 | Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks | May 16, 1995 | Issued |
Array
(
[id] => 3625867
[patent_doc_number] => 05614840
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors'
[patent_app_type] => 1
[patent_app_number] => 8/443119
[patent_app_country] => US
[patent_app_date] => 1995-05-17
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[pdf_file] => patents/05/614/05614840.pdf
[firstpage_image] =>[orig_patent_app_number] => 443119
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/443119 | Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors | May 16, 1995 | Issued |
Array
(
[id] => 3543048
[patent_doc_number] => 05495183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-27
[patent_title] => 'Level conversion circuitry for a semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/440335
[patent_app_country] => US
[patent_app_date] => 1995-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/495/05495183.pdf
[firstpage_image] =>[orig_patent_app_number] => 440335
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/440335 | Level conversion circuitry for a semiconductor integrated circuit | May 11, 1995 | Issued |
08/438613 | MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR SEMICONDUCTOR "AND" GATE DEVICE | May 9, 1995 | Abandoned |