Bao Thuy L Nguyen
Examiner (ID: 2543)
Most Active Art Unit | 1641 |
Art Unit(s) | 1641, 1677, 1802 |
Total Applications | 986 |
Issued Applications | 447 |
Pending Applications | 220 |
Abandoned Applications | 283 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3837673
[patent_doc_number] => 05739702
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Bus hold circuit'
[patent_app_type] => 1
[patent_app_number] => 8/704995
[patent_app_country] => US
[patent_app_date] => 1996-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 5114
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/739/05739702.pdf
[firstpage_image] =>[orig_patent_app_number] => 704995
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/704995 | Bus hold circuit | Aug 28, 1996 | Issued |
Array
(
[id] => 3734277
[patent_doc_number] => 05670897
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'High speed mask register for a configurable cellular array'
[patent_app_type] => 1
[patent_app_number] => 8/711225
[patent_app_country] => US
[patent_app_date] => 1996-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 61
[patent_no_of_words] => 27732
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/670/05670897.pdf
[firstpage_image] =>[orig_patent_app_number] => 711225
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/711225 | High speed mask register for a configurable cellular array | Aug 26, 1996 | Issued |
Array
(
[id] => 3887036
[patent_doc_number] => 05798656
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Match register with duplicate decoders'
[patent_app_type] => 1
[patent_app_number] => 8/711221
[patent_app_country] => US
[patent_app_date] => 1996-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 61
[patent_no_of_words] => 27760
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/798/05798656.pdf
[firstpage_image] =>[orig_patent_app_number] => 711221
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/711221 | Match register with duplicate decoders | Aug 26, 1996 | Issued |
Array
(
[id] => 3836818
[patent_doc_number] => 05760601
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Transmission line driver circuit for matching transmission line characteristic impedance'
[patent_app_type] => 1
[patent_app_number] => 8/703318
[patent_app_country] => US
[patent_app_date] => 1996-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2615
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/760/05760601.pdf
[firstpage_image] =>[orig_patent_app_number] => 703318
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/703318 | Transmission line driver circuit for matching transmission line characteristic impedance | Aug 25, 1996 | Issued |
Array
(
[id] => 3767049
[patent_doc_number] => 05742183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Level shift semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/702924
[patent_app_country] => US
[patent_app_date] => 1996-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 5579
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742183.pdf
[firstpage_image] =>[orig_patent_app_number] => 702924
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/702924 | Level shift semiconductor device | Aug 25, 1996 | Issued |
Array
(
[id] => 3822843
[patent_doc_number] => 05789936
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Circuit for sensing a communication state'
[patent_app_type] => 1
[patent_app_number] => 8/703009
[patent_app_country] => US
[patent_app_date] => 1996-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3166
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/789/05789936.pdf
[firstpage_image] =>[orig_patent_app_number] => 703009
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/703009 | Circuit for sensing a communication state | Aug 25, 1996 | Issued |
Array
(
[id] => 3866924
[patent_doc_number] => 05793223
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Reference signal generation in a switched current source transmission line driver/receiver system'
[patent_app_type] => 1
[patent_app_number] => 8/703317
[patent_app_country] => US
[patent_app_date] => 1996-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3367
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/793/05793223.pdf
[firstpage_image] =>[orig_patent_app_number] => 703317
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/703317 | Reference signal generation in a switched current source transmission line driver/receiver system | Aug 25, 1996 | Issued |
Array
(
[id] => 3693264
[patent_doc_number] => 05696455
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Reconfigurable programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/697103
[patent_app_country] => US
[patent_app_date] => 1996-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5173
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696455.pdf
[firstpage_image] =>[orig_patent_app_number] => 697103
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/697103 | Reconfigurable programmable logic device | Aug 18, 1996 | Issued |
Array
(
[id] => 3799109
[patent_doc_number] => 05726588
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-10
[patent_title] => 'Differential-to-CMOS level converter having cross-over voltage adjustment'
[patent_app_type] => 1
[patent_app_number] => 8/698306
[patent_app_country] => US
[patent_app_date] => 1996-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4522
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/726/05726588.pdf
[firstpage_image] =>[orig_patent_app_number] => 698306
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/698306 | Differential-to-CMOS level converter having cross-over voltage adjustment | Aug 14, 1996 | Issued |
Array
(
[id] => 3666631
[patent_doc_number] => 05656947
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Low noise digital output buffer'
[patent_app_type] => 1
[patent_app_number] => 8/680902
[patent_app_country] => US
[patent_app_date] => 1996-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 4420
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/656/05656947.pdf
[firstpage_image] =>[orig_patent_app_number] => 680902
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/680902 | Low noise digital output buffer | Jul 15, 1996 | Issued |
Array
(
[id] => 3767078
[patent_doc_number] => 05742185
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Data bus drive circuit for semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/670840
[patent_app_country] => US
[patent_app_date] => 1996-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2650
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742185.pdf
[firstpage_image] =>[orig_patent_app_number] => 670840
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/670840 | Data bus drive circuit for semiconductor memory device | Jun 27, 1996 | Issued |
Array
(
[id] => 3782288
[patent_doc_number] => 05808481
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Output swing clamp for USB differential buffer'
[patent_app_type] => 1
[patent_app_number] => 8/670879
[patent_app_country] => US
[patent_app_date] => 1996-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7579
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808481.pdf
[firstpage_image] =>[orig_patent_app_number] => 670879
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/670879 | Output swing clamp for USB differential buffer | Jun 27, 1996 | Issued |
Array
(
[id] => 3831592
[patent_doc_number] => 05731711
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Integrated circuit chip with adaptive input-output port'
[patent_app_type] => 1
[patent_app_number] => 8/672494
[patent_app_country] => US
[patent_app_date] => 1996-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 6898
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/731/05731711.pdf
[firstpage_image] =>[orig_patent_app_number] => 672494
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/672494 | Integrated circuit chip with adaptive input-output port | Jun 25, 1996 | Issued |
Array
(
[id] => 3964862
[patent_doc_number] => 05983170
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'System and method for generating semantic analysis of textual information'
[patent_app_type] => 1
[patent_app_number] => 8/670809
[patent_app_country] => US
[patent_app_date] => 1996-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 5502
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/983/05983170.pdf
[firstpage_image] =>[orig_patent_app_number] => 670809
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/670809 | System and method for generating semantic analysis of textual information | Jun 24, 1996 | Issued |
Array
(
[id] => 3905697
[patent_doc_number] => 05751164
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Programmable logic device with multi-level power control'
[patent_app_type] => 1
[patent_app_number] => 8/668896
[patent_app_country] => US
[patent_app_date] => 1996-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5264
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[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/751/05751164.pdf
[firstpage_image] =>[orig_patent_app_number] => 668896
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/668896 | Programmable logic device with multi-level power control | Jun 23, 1996 | Issued |
Array
(
[id] => 3882170
[patent_doc_number] => 05825201
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Programming architecture for a programmable integrated circuit employing antifuses'
[patent_app_type] => 1
[patent_app_number] => 8/667702
[patent_app_country] => US
[patent_app_date] => 1996-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 46
[patent_no_of_words] => 8727
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 348
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825201.pdf
[firstpage_image] =>[orig_patent_app_number] => 667702
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/667702 | Programming architecture for a programmable integrated circuit employing antifuses | Jun 20, 1996 | Issued |
Array
(
[id] => 3768597
[patent_doc_number] => 05844423
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Half-full flag generator for synchronous FIFOs'
[patent_app_type] => 1
[patent_app_number] => 8/666751
[patent_app_country] => US
[patent_app_date] => 1996-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2865
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/844/05844423.pdf
[firstpage_image] =>[orig_patent_app_number] => 666751
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/666751 | Half-full flag generator for synchronous FIFOs | Jun 18, 1996 | Issued |
Array
(
[id] => 3866939
[patent_doc_number] => 05793224
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Voltage generator for antifuse programming'
[patent_app_type] => 1
[patent_app_number] => 8/666617
[patent_app_country] => US
[patent_app_date] => 1996-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1679
[patent_no_of_claims] => 18
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/793/05793224.pdf
[firstpage_image] =>[orig_patent_app_number] => 666617
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/666617 | Voltage generator for antifuse programming | Jun 17, 1996 | Issued |
Array
(
[id] => 3885066
[patent_doc_number] => 05729156
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'ECL to CMOS level translator using delayed feedback for high speed BiCMOS applications'
[patent_app_type] => 1
[patent_app_number] => 8/664875
[patent_app_country] => US
[patent_app_date] => 1996-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3512
[patent_no_of_claims] => 8
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[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/729/05729156.pdf
[firstpage_image] =>[orig_patent_app_number] => 664875
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/664875 | ECL to CMOS level translator using delayed feedback for high speed BiCMOS applications | Jun 17, 1996 | Issued |
Array
(
[id] => 3767035
[patent_doc_number] => 05742182
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Symmetric selector circuit for event logic'
[patent_app_type] => 1
[patent_app_number] => 8/665154
[patent_app_country] => US
[patent_app_date] => 1996-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2571
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742182.pdf
[firstpage_image] =>[orig_patent_app_number] => 665154
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/665154 | Symmetric selector circuit for event logic | Jun 12, 1996 | Issued |