Search

Christopher E Dunay

Examiner (ID: 1458, Phone: (571)270-1222 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875
Total Applications
722
Issued Applications
487
Pending Applications
67
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16574994 [patent_doc_number] => 10896922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Imaging apparatus, imaging system, moving object, and method for manufacturing imaging apparatus [patent_app_type] => utility [patent_app_number] => 15/996313 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 9119 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15996313 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/996313
Imaging apparatus, imaging system, moving object, and method for manufacturing imaging apparatus May 31, 2018 Issued
Array ( [id] => 15906033 [patent_doc_number] => 20200152537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 16/617307 [patent_app_country] => US [patent_app_date] => 2018-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16617307 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/617307
Semiconductor apparatus May 27, 2018 Issued
Array ( [id] => 13392977 [patent_doc_number] => 20180248031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/964026 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964026 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964026
Method for manufacturing thin film transistor substrate Apr 25, 2018 Issued
Array ( [id] => 14938277 [patent_doc_number] => 20190304777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => METHOD FOR FORMING HARD MASK [patent_app_type] => utility [patent_app_number] => 15/964031 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964031 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964031
METHOD FOR FORMING HARD MASK Apr 25, 2018 Abandoned
Array ( [id] => 16249494 [patent_doc_number] => 10748869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Protective layer for contact pads in fan-out interconnect structure and method of forming same [patent_app_type] => utility [patent_app_number] => 15/938451 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 4704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938451 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/938451
Protective layer for contact pads in fan-out interconnect structure and method of forming same Mar 27, 2018 Issued
Array ( [id] => 14690047 [patent_doc_number] => 20190244139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => USING META-LEARNING FOR AUTOMATIC GRADIENT-BASED HYPERPARAMETER OPTIMIZATION FOR MACHINE LEARNING AND DEEP LEARNING MODELS [patent_app_type] => utility [patent_app_number] => 15/914883 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914883 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914883
USING META-LEARNING FOR AUTOMATIC GRADIENT-BASED HYPERPARAMETER OPTIMIZATION FOR MACHINE LEARNING AND DEEP LEARNING MODELS Mar 6, 2018 Pending
Array ( [id] => 16238745 [patent_doc_number] => 20200255979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => GALLIUM NITRIDE CRYSTAL SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/651716 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16651716 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/651716
Gallium nitride crystal substrate Feb 22, 2018 Issued
Array ( [id] => 14267753 [patent_doc_number] => 10283448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/887142 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 4623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887142 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/887142
Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same Feb 1, 2018 Issued
Array ( [id] => 14658721 [patent_doc_number] => 20190236489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => METHOD AND SYSTEM FOR INDUSTRIAL PARTS SEARCH, HARMONIZATION, AND RATIONALIZATION THROUGH DIGITAL TWIN TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 15/883895 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883895 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883895
METHOD AND SYSTEM FOR INDUSTRIAL PARTS SEARCH, HARMONIZATION, AND RATIONALIZATION THROUGH DIGITAL TWIN TECHNOLOGY Jan 29, 2018 Abandoned
Array ( [id] => 15608043 [patent_doc_number] => 10585074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Method of fabricating a MEMS and/or NEMS structure comprising at least two elements suspended from a support at different distances from said support [patent_app_type] => utility [patent_app_number] => 15/873136 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 33 [patent_no_of_words] => 3716 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873136 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873136
Method of fabricating a MEMS and/or NEMS structure comprising at least two elements suspended from a support at different distances from said support Jan 16, 2018 Issued
Array ( [id] => 13755285 [patent_doc_number] => 10170597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Method for forming flash memory unit [patent_app_type] => utility [patent_app_number] => 15/872998 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5607 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15872998 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/872998
Method for forming flash memory unit Jan 16, 2018 Issued
Array ( [id] => 17409446 [patent_doc_number] => 11250336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Distributed and contextualized artificial intelligence inference service [patent_app_type] => utility [patent_app_number] => 15/857087 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17072 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857087 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857087
Distributed and contextualized artificial intelligence inference service Dec 27, 2017 Issued
Array ( [id] => 13862041 [patent_doc_number] => 10192745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Method for manufacturing a layer stack from a p+-substrate, a p--layer, an n--layer and a third layer [patent_app_type] => utility [patent_app_number] => 15/845530 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2010 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845530 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845530
Method for manufacturing a layer stack from a p+-substrate, a p--layer, an n--layer and a third layer Dec 17, 2017 Issued
Array ( [id] => 14475629 [patent_doc_number] => 20190189462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SELF-ASSEMBLED MONOLAYERS AS AN ETCHANT IN ATOMIC LAYER ETCHING [patent_app_type] => utility [patent_app_number] => 15/845910 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845910
Self-assembled monolayers as an etchant in atomic layer etching Dec 17, 2017 Issued
Array ( [id] => 15234005 [patent_doc_number] => 10504732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Impurity diffusion agent composition and method for manufacturing semiconductor substrate [patent_app_type] => utility [patent_app_number] => 15/845015 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11793 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845015 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845015
Impurity diffusion agent composition and method for manufacturing semiconductor substrate Dec 17, 2017 Issued
Array ( [id] => 12849277 [patent_doc_number] => 20180174932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => TRANSFER PRINTED DEVICE REPAIR [patent_app_type] => utility [patent_app_number] => 15/845791 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845791
Transfer printed device repair Dec 17, 2017 Issued
Array ( [id] => 13293313 [patent_doc_number] => 10157857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Methods for fabricating semiconductor shielding structures [patent_app_type] => utility [patent_app_number] => 15/845256 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845256 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845256
Methods for fabricating semiconductor shielding structures Dec 17, 2017 Issued
Array ( [id] => 12872620 [patent_doc_number] => 20180182715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SEMICONDUCTOR PACKAGE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 15/845803 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845803
Semiconductor package manufacturing method Dec 17, 2017 Issued
Array ( [id] => 15427613 [patent_doc_number] => 10546745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Semiconductor processing method [patent_app_type] => utility [patent_app_number] => 15/844905 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3678 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844905 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844905
Semiconductor processing method Dec 17, 2017 Issued
Array ( [id] => 15427705 [patent_doc_number] => 10546792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Method for manufacturing a semiconductor product wafer [patent_app_type] => utility [patent_app_number] => 15/845361 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2749 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845361 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845361
Method for manufacturing a semiconductor product wafer Dec 17, 2017 Issued
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