Search

Danielle B Henkel

Examiner (ID: 232, Phone: (571)270-5505 , Office: P/1799 )

Most Active Art Unit
1799
Art Unit(s)
1799, 1797, 1775
Total Applications
633
Issued Applications
314
Pending Applications
53
Abandoned Applications
266

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4651680 [patent_doc_number] => 20080038936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'METHOD TO FORM ULTRA HIGH QUALITY SILICON-CONTAINING COMPOUND LAYERS' [patent_app_type] => utility [patent_app_number] => 11/877480 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13967 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038936.pdf [firstpage_image] =>[orig_patent_app_number] => 11877480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877480
Method to form ultra high quality silicon-containing compound layers Oct 22, 2007 Issued
Array ( [id] => 4648763 [patent_doc_number] => 20080036018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'METHOD OF FABRICATING SPACERS AND CLEANING METHOD OF POST-ETCHING AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/874683 [patent_app_country] => US [patent_app_date] => 2007-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2808 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20080036018.pdf [firstpage_image] =>[orig_patent_app_number] => 11874683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/874683
METHOD OF FABRICATING SPACERS AND CLEANING METHOD OF POST-ETCHING AND SEMICONDUCTOR DEVICE Oct 17, 2007 Abandoned
Array ( [id] => 4922067 [patent_doc_number] => 20080070382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'FIXING APPARATUS FOR SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 11/858821 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2115 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20080070382.pdf [firstpage_image] =>[orig_patent_app_number] => 11858821 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/858821
FIXING APPARATUS FOR SEMICONDUCTOR WAFER Sep 19, 2007 Abandoned
Array ( [id] => 7730674 [patent_doc_number] => 08101938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method' [patent_app_type] => utility [patent_app_number] => 11/903236 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/101/08101938.pdf [firstpage_image] =>[orig_patent_app_number] => 11903236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/903236
Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method Sep 19, 2007 Issued
Array ( [id] => 5081701 [patent_doc_number] => 20070271751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'METHOD OF FORMING A RELIABLE ELECTROCHEMICAL CAPACITOR' [patent_app_type] => utility [patent_app_number] => 11/837375 [patent_app_country] => US [patent_app_date] => 2007-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271751.pdf [firstpage_image] =>[orig_patent_app_number] => 11837375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/837375
METHOD OF FORMING A RELIABLE ELECTROCHEMICAL CAPACITOR Aug 9, 2007 Abandoned
Array ( [id] => 4772074 [patent_doc_number] => 20080057732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'METHOD FOR MANUFACTURING SILICON SUBSTRATE, METHOD FOR MANUFACTURING DROPLET DISCHARGING HEAD, AND METHOD FOR MANUFACTURING DROPLET DISCHARGING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/833821 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9355 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057732.pdf [firstpage_image] =>[orig_patent_app_number] => 11833821 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833821
METHOD FOR MANUFACTURING SILICON SUBSTRATE, METHOD FOR MANUFACTURING DROPLET DISCHARGING HEAD, AND METHOD FOR MANUFACTURING DROPLET DISCHARGING APPARATUS Aug 2, 2007 Abandoned
Array ( [id] => 4729097 [patent_doc_number] => 20080047116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'METHOD OF PRODUCING ELECTROLYTIC CAPACITOR' [patent_app_type] => utility [patent_app_number] => 11/828045 [patent_app_country] => US [patent_app_date] => 2007-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5285 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20080047116.pdf [firstpage_image] =>[orig_patent_app_number] => 11828045 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/828045
METHOD OF PRODUCING ELECTROLYTIC CAPACITOR Jul 24, 2007 Abandoned
Array ( [id] => 5225188 [patent_doc_number] => 20070254454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'PROCESS FOR BONDING AND ELECTRICALLY CONNECTING MICROSYSTEMS INTEGRATED IN SEVERAL DISTINCT SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 11/766654 [patent_app_country] => US [patent_app_date] => 2007-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2703 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20070254454.pdf [firstpage_image] =>[orig_patent_app_number] => 11766654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/766654
Process for bonding and electrically connecting microsystems integrated in several distinct substrates Jun 20, 2007 Issued
Array ( [id] => 5165663 [patent_doc_number] => 20070287250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Method for fabricating a semiconductor device having an insulation film with reduced water content' [patent_app_type] => utility [patent_app_number] => 11/798366 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9121 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20070287250.pdf [firstpage_image] =>[orig_patent_app_number] => 11798366 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/798366
Method for fabricating a semiconductor device having an insulation film with reduced water content May 13, 2007 Issued
Array ( [id] => 5259183 [patent_doc_number] => 20070212815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'SEALED THREE DIMENSIONAL METAL BONDED INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/747846 [patent_app_country] => US [patent_app_date] => 2007-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3714 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20070212815.pdf [firstpage_image] =>[orig_patent_app_number] => 11747846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/747846
SEALED THREE DIMENSIONAL METAL BONDED INTEGRATED CIRCUITS May 10, 2007 Abandoned
Array ( [id] => 4719585 [patent_doc_number] => 20080242108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/730551 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242108.pdf [firstpage_image] =>[orig_patent_app_number] => 11730551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730551
Method for fabricating semiconductor device Apr 1, 2007 Abandoned
Array ( [id] => 5175211 [patent_doc_number] => 20070176269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Multi-chips module package and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/730442 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3212 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176269.pdf [firstpage_image] =>[orig_patent_app_number] => 11730442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730442
Multi-chips module package and manufacturing method thereof Apr 1, 2007 Abandoned
Array ( [id] => 4619608 [patent_doc_number] => 07999328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Isolation trench having first and second trench areas of different widths' [patent_app_type] => utility [patent_app_number] => 11/714220 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3595 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/999/07999328.pdf [firstpage_image] =>[orig_patent_app_number] => 11714220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714220
Isolation trench having first and second trench areas of different widths Mar 5, 2007 Issued
Array ( [id] => 902934 [patent_doc_number] => 07335542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Semiconductor device with mushroom electrode and manufacture method thereof' [patent_app_type] => utility [patent_app_number] => 11/713599 [patent_app_country] => US [patent_app_date] => 2007-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 44 [patent_no_of_words] => 8153 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/335/07335542.pdf [firstpage_image] =>[orig_patent_app_number] => 11713599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/713599
Semiconductor device with mushroom electrode and manufacture method thereof Mar 4, 2007 Issued
Array ( [id] => 5188654 [patent_doc_number] => 20070166962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Methods of forming layers comprising epitaxial silicon' [patent_app_type] => utility [patent_app_number] => 11/712151 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5190 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20070166962.pdf [firstpage_image] =>[orig_patent_app_number] => 11712151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/712151
Methods of forming layers comprising epitaxial silicon Feb 27, 2007 Issued
Array ( [id] => 4685698 [patent_doc_number] => 20080029879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Structure and method of making lidded chips' [patent_app_type] => utility [patent_app_number] => 11/711595 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 70 [patent_no_of_words] => 48615 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029879.pdf [firstpage_image] =>[orig_patent_app_number] => 11711595 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711595
Structure and method of making lidded chips Feb 26, 2007 Abandoned
Array ( [id] => 4599298 [patent_doc_number] => 07977122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Fluidic device containing 3D structures' [patent_app_type] => utility [patent_app_number] => 11/669351 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4045 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/977/07977122.pdf [firstpage_image] =>[orig_patent_app_number] => 11669351 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669351
Fluidic device containing 3D structures Jan 30, 2007 Issued
Array ( [id] => 42602 [patent_doc_number] => 07781293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Semiconductor device and method of fabricating the same including trenches of different aspect ratios' [patent_app_type] => utility [patent_app_number] => 11/611030 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3811 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/781/07781293.pdf [firstpage_image] =>[orig_patent_app_number] => 11611030 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/611030
Semiconductor device and method of fabricating the same including trenches of different aspect ratios Dec 13, 2006 Issued
Array ( [id] => 5095735 [patent_doc_number] => 20070117344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING A CRYSTAL SEMICONDUCTOR LAYER, ITS FABRICATION AND ITS OPERATION' [patent_app_type] => utility [patent_app_number] => 11/561151 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5796 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117344.pdf [firstpage_image] =>[orig_patent_app_number] => 11561151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561151
Semiconductor device including a crystal semiconductor layer, its fabrication and its operation Nov 16, 2006 Issued
Array ( [id] => 5095652 [patent_doc_number] => 20070117261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Multilayer printed wiring board and method for producing the same' [patent_app_type] => utility [patent_app_number] => 11/594831 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13226 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117261.pdf [firstpage_image] =>[orig_patent_app_number] => 11594831 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/594831
Multilayer printed wiring board and method for producing the same Nov 8, 2006 Abandoned
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