Search

James S Bergin

Examiner (ID: 145, Phone: (571)272-6872 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
2164, 3616, 3643, 3624, 3641
Total Applications
1752
Issued Applications
1299
Pending Applications
160
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11614722 [patent_doc_number] => 09652579 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-16 [patent_title] => 'Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs' [patent_app_type] => utility [patent_app_number] => 14/675426 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 15398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675426 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675426
Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs Mar 30, 2015 Issued
Array ( [id] => 10195012 [patent_doc_number] => 09223922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Semiconductor device design method' [patent_app_type] => utility [patent_app_number] => 14/658749 [patent_app_country] => US [patent_app_date] => 2015-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14658749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/658749
Semiconductor device design method Mar 15, 2015 Issued
Array ( [id] => 10424797 [patent_doc_number] => 20150309808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'Method and System on Chip (SoC) for Adapting a Reconfigurable Hardware for an Application in Runtime' [patent_app_type] => utility [patent_app_number] => 14/639141 [patent_app_country] => US [patent_app_date] => 2015-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4746 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14639141 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/639141
Method and System on Chip (SoC) for Adapting a Reconfigurable Hardware for an Application in Runtime Mar 4, 2015 Abandoned
Array ( [id] => 11285735 [patent_doc_number] => 09501590 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-22 [patent_title] => 'Systems and methods for testing integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 14/639014 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7789 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14639014 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/639014
Systems and methods for testing integrated circuit designs Mar 3, 2015 Issued
Array ( [id] => 10425149 [patent_doc_number] => 20150310159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'COMPUTER-IMPLEMENTED VERIFICATION SYSTEM FOR PERFORMING A FUNCTIONAL VERIFICATION OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/638475 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8306 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14638475 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/638475
Computer-implemented verification system for performing a functional verification of an integrated circuit Mar 3, 2015 Issued
Array ( [id] => 11239251 [patent_doc_number] => 09465896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-11 [patent_title] => 'Systems and methods for testing integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 14/639029 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8343 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14639029 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/639029
Systems and methods for testing integrated circuit designs Mar 3, 2015 Issued
Array ( [id] => 11042403 [patent_doc_number] => 20160239359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'PERSISTENT COMMAND PARAMETER TABLE FOR PRE-SILICON DEVICE TESTING' [patent_app_type] => utility [patent_app_number] => 14/620431 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620431 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620431
Persistent command parameter table for pre-silicon device testing Feb 11, 2015 Issued
Array ( [id] => 10269334 [patent_doc_number] => 20150154331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/616135 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14616135 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/616135
ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS Feb 5, 2015 Abandoned
Array ( [id] => 10252772 [patent_doc_number] => 20150137768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'CHARGE RATE OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 14/605043 [patent_app_country] => US [patent_app_date] => 2015-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4489 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14605043 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/605043
Charge rate optimization Jan 25, 2015 Issued
Array ( [id] => 10238704 [patent_doc_number] => 20150123699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs' [patent_app_type] => utility [patent_app_number] => 14/595251 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595251 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/595251
System and method for functional verification of multi-die 3D ICs Jan 12, 2015 Issued
Array ( [id] => 10228492 [patent_doc_number] => 20150113485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'PATTERN DATA GENERATION METHOD, PATTERN VERIFICATION METHOD, AND OPTICAL IMAGE CALCULATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/578719 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14493 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578719 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/578719
Pattern data generation method, pattern verification method, and optical image calculation method Dec 21, 2014 Issued
Array ( [id] => 10228490 [patent_doc_number] => 20150113484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'METHODS OF GENERATING CIRCUIT LAYOUTS THAT ARE TO BE MANUFACTURED USING SADP ROUTING TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 14/578717 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9372 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578717 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/578717
Methods of generating circuit layouts that are to be manufactured using SADP routing techniques Dec 21, 2014 Issued
Array ( [id] => 10293442 [patent_doc_number] => 20150178441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'METHOD FOR WIRE WIDENING IN CIRCUIT ROUTING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/576117 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7571 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576117
Method for wire widening in circuit routing system Dec 17, 2014 Issued
Array ( [id] => 10623695 [patent_doc_number] => 09342638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-17 [patent_title] => 'Method and system to perform performance checks' [patent_app_type] => utility [patent_app_number] => 14/574145 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7935 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14574145 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/574145
Method and system to perform performance checks Dec 16, 2014 Issued
Array ( [id] => 10984882 [patent_doc_number] => 20160181828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'DEVICE AND METHOD FOR CONTROLLING BATTERY' [patent_app_type] => utility [patent_app_number] => 14/573325 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14573325 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/573325
DEVICE AND METHOD FOR CONTROLLING BATTERY Dec 16, 2014 Abandoned
Array ( [id] => 11488790 [patent_doc_number] => 09594861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-14 [patent_title] => 'Method and system to perform equivalency checks' [patent_app_type] => utility [patent_app_number] => 14/574113 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7809 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14574113 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/574113
Method and system to perform equivalency checks Dec 16, 2014 Issued
Array ( [id] => 13654293 [patent_doc_number] => 09853471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Mechanism for extending cycle life of a battery [patent_app_type] => utility [patent_app_number] => 14/572757 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14572757 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/572757
Mechanism for extending cycle life of a battery Dec 15, 2014 Issued
Array ( [id] => 11586346 [patent_doc_number] => 09641001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Electronic apparatus and method' [patent_app_type] => utility [patent_app_number] => 14/571879 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9879 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14571879 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/571879
Electronic apparatus and method Dec 15, 2014 Issued
Array ( [id] => 11525041 [patent_doc_number] => 09608457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Charging device and method for commonly charging multiple digital electronic devices' [patent_app_type] => utility [patent_app_number] => 14/571366 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4992 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14571366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/571366
Charging device and method for commonly charging multiple digital electronic devices Dec 15, 2014 Issued
Array ( [id] => 10210875 [patent_doc_number] => 20150095867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 14/567383 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567383 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567383
Semiconductor circuit design method, memory compiler and computer program product Dec 10, 2014 Issued
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