Search

James S Bergin

Examiner (ID: 145, Phone: (571)272-6872 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
2164, 3616, 3643, 3624, 3641
Total Applications
1752
Issued Applications
1299
Pending Applications
160
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10221787 [patent_doc_number] => 20150106780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'SEMICONDUCTOR DEVICE RELIABILITY MODEL AND METHODOLOGIES FOR USE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/551693 [patent_app_country] => US [patent_app_date] => 2014-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12434 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14551693 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/551693
Semiconductor device reliability model and methodologies for use thereof Nov 23, 2014 Issued
Array ( [id] => 11411004 [patent_doc_number] => 09558308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Compiler for closed-loop 1×N VLSI design' [patent_app_type] => utility [patent_app_number] => 14/537685 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 16621 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14537685 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/537685
Compiler for closed-loop 1×N VLSI design Nov 9, 2014 Issued
Array ( [id] => 9866868 [patent_doc_number] => 20150046887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'RETARGETING SEMICONDUCTOR DEVICE SHAPES FOR MULTIPLE PATTERNING PROCESSES' [patent_app_type] => utility [patent_app_number] => 14/525833 [patent_app_country] => US [patent_app_date] => 2014-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3719 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14525833 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/525833
Retargeting semiconductor device shapes for multiple patterning processes Oct 27, 2014 Issued
Array ( [id] => 11064161 [patent_doc_number] => 20160261124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'BATTERY MANAGEMENT SYSTEM FOR TRANSMITTING SECONDARY PROTECTION SIGNAL AND DIAGNOSIS SIGNAL USING A SMALL NUMBER OF INSULATION ELEMENTS' [patent_app_type] => utility [patent_app_number] => 14/442158 [patent_app_country] => US [patent_app_date] => 2014-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4713 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14442158 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/442158
Battery management system for transmitting secondary protection signal and diagnosis signal using a small number of insulation elements Oct 15, 2014 Issued
Array ( [id] => 11064162 [patent_doc_number] => 20160261125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'BATTERY MANAGEMENT SYSTEM FOR TRANSMITTING SECONDARY PROTECTION SIGNAL AND DIAGNOSIS SIGNAL USING A SMALL NUMBER OF INSULATION ELEMENTS' [patent_app_type] => utility [patent_app_number] => 14/442216 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5288 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14442216 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/442216
Battery management system for transmitting secondary protection signal and diagnosis signal using a small number of insulation elements Oct 14, 2014 Issued
Array ( [id] => 10486801 [patent_doc_number] => 20150371821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'Method of Fabricating an Integrated Circuit with a Pattern Density-Outlier-Treatment for Optimized Pattern Density Uniformity' [patent_app_type] => utility [patent_app_number] => 14/483893 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4023 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483893 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/483893
Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity Sep 10, 2014 Issued
Array ( [id] => 10171288 [patent_doc_number] => 09201998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-01 [patent_title] => 'Topography simulation apparatus, topography simulation method and recording medium' [patent_app_type] => utility [patent_app_number] => 14/482502 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 8357 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482502 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/482502
Topography simulation apparatus, topography simulation method and recording medium Sep 9, 2014 Issued
Array ( [id] => 10725699 [patent_doc_number] => 20160071847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'HALF NODE SCALING FOR VERTICAL STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/480156 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7427 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480156 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480156
Half node scaling for vertical structures Sep 7, 2014 Issued
Array ( [id] => 10724692 [patent_doc_number] => 20160070840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS' [patent_app_type] => utility [patent_app_number] => 14/477976 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11333 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477976 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477976
Integrated circuit design changes using through-silicon vias Sep 4, 2014 Issued
Array ( [id] => 10717014 [patent_doc_number] => 20160063161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'RESET VERIFICATION' [patent_app_type] => utility [patent_app_number] => 14/476384 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476384 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/476384
Reset verification Sep 2, 2014 Issued
Array ( [id] => 10184119 [patent_doc_number] => 09213799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-15 [patent_title] => 'Systematic defect analysis method and machine readable media' [patent_app_type] => utility [patent_app_number] => 14/459307 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2667 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459307 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459307
Systematic defect analysis method and machine readable media Aug 12, 2014 Issued
Array ( [id] => 9859736 [patent_doc_number] => 20150039753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'SYSTEM AND METHOD FOR CAPACITY PLANNING FOR SYSTEMS WITH MULTITHREADED MULTICORE MULTIPROCESSOR RESOURCES' [patent_app_type] => utility [patent_app_number] => 14/336703 [patent_app_country] => US [patent_app_date] => 2014-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9558 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14336703 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/336703
System and method for capacity planning for systems with multithreaded multicore multiprocessor resources Jul 20, 2014 Issued
Array ( [id] => 9866870 [patent_doc_number] => 20150046889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'STATE GROUPING FOR ELEMENT UTILIZATION' [patent_app_type] => utility [patent_app_number] => 14/335537 [patent_app_country] => US [patent_app_date] => 2014-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14335537 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/335537
State grouping for element utilization Jul 17, 2014 Issued
Array ( [id] => 10079183 [patent_doc_number] => 09117031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Generating interface adjustment signals in a device-to-device interconnection system' [patent_app_type] => utility [patent_app_number] => 14/329791 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 19464 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329791 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329791
Generating interface adjustment signals in a device-to-device interconnection system Jul 10, 2014 Issued
Array ( [id] => 10524789 [patent_doc_number] => 09251304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Circuit design evaluation with compact multi-waveform representations' [patent_app_type] => utility [patent_app_number] => 14/327658 [patent_app_country] => US [patent_app_date] => 2014-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 23144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327658 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/327658
Circuit design evaluation with compact multi-waveform representations Jul 9, 2014 Issued
Array ( [id] => 10151054 [patent_doc_number] => 09183345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Apparatus and method for generating a power delivery network' [patent_app_type] => utility [patent_app_number] => 14/326070 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3224 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326070 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326070
Apparatus and method for generating a power delivery network Jul 7, 2014 Issued
Array ( [id] => 10969784 [patent_doc_number] => 20140372817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'AUTOMATED CIRCUIT TRIPLICATION METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/308471 [patent_app_country] => US [patent_app_date] => 2014-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9351 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14308471 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/308471
Automated circuit triplication method and system Jun 17, 2014 Issued
Array ( [id] => 10462649 [patent_doc_number] => 20150347664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'SYSTEM FOR AND METHOD OF SEMICONDUCTOR FAULT DETECTION' [patent_app_type] => utility [patent_app_number] => 14/291286 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14291286 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/291286
System for and method of semiconductor fault detection May 29, 2014 Issued
Array ( [id] => 9940930 [patent_doc_number] => 08990762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Semiconductor device design method, system and computer program product' [patent_app_type] => utility [patent_app_number] => 14/291285 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14291285 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/291285
Semiconductor device design method, system and computer program product May 29, 2014 Issued
Array ( [id] => 9746590 [patent_doc_number] => 20140282310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD OF PERFORMING CIRCUIT SIMULATION AND GENERATING CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 14/291125 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14291125 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/291125
Method of performing circuit simulation and generating circuit layout May 29, 2014 Issued
Menu