Search

James S Bergin

Examiner (ID: 145, Phone: (571)272-6872 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
2164, 3616, 3643, 3624, 3641
Total Applications
1752
Issued Applications
1299
Pending Applications
160
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10052706 [patent_doc_number] => 09092586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-28 [patent_title] => 'Version management mechanism for fluid guard ring PCells' [patent_app_type] => utility [patent_app_number] => 14/292661 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3843 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14292661 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/292661
Version management mechanism for fluid guard ring PCells May 29, 2014 Issued
Array ( [id] => 12257430 [patent_doc_number] => 09929586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Battery pack and portable electronic apparatus' [patent_app_type] => utility [patent_app_number] => 14/894497 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3972 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14894497 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/894497
Battery pack and portable electronic apparatus May 27, 2014 Issued
Array ( [id] => 11432053 [patent_doc_number] => 09570378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Semiconductor device including dummy pattern' [patent_app_type] => utility [patent_app_number] => 14/283050 [patent_app_country] => US [patent_app_date] => 2014-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 7666 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14283050 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/283050
Semiconductor device including dummy pattern May 19, 2014 Issued
Array ( [id] => 10085489 [patent_doc_number] => 09122837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-01 [patent_title] => 'Validating integrated circuit simulation results' [patent_app_type] => utility [patent_app_number] => 14/271189 [patent_app_country] => US [patent_app_date] => 2014-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271189 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271189
Validating integrated circuit simulation results May 5, 2014 Issued
Array ( [id] => 10562748 [patent_doc_number] => 09286426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Method and apparatus for testing' [patent_app_type] => utility [patent_app_number] => 14/259163 [patent_app_country] => US [patent_app_date] => 2014-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7554 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14259163 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/259163
Method and apparatus for testing Apr 22, 2014 Issued
Array ( [id] => 9926475 [patent_doc_number] => 08984462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-17 [patent_title] => 'Physical optimization for timing closure for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/249601 [patent_app_country] => US [patent_app_date] => 2014-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14249601 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/249601
Physical optimization for timing closure for an integrated circuit Apr 9, 2014 Issued
Array ( [id] => 11299892 [patent_doc_number] => 09507900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Method and apparatus for decomposing functions in a configurable IC' [patent_app_type] => utility [patent_app_number] => 14/246970 [patent_app_country] => US [patent_app_date] => 2014-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 51 [patent_no_of_words] => 18452 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14246970 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/246970
Method and apparatus for decomposing functions in a configurable IC Apr 6, 2014 Issued
Array ( [id] => 10576215 [patent_doc_number] => 09298862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-29 [patent_title] => 'Resource sharing workflows within executable graphical models' [patent_app_type] => utility [patent_app_number] => 14/245629 [patent_app_country] => US [patent_app_date] => 2014-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 18024 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14245629 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/245629
Resource sharing workflows within executable graphical models Apr 3, 2014 Issued
Array ( [id] => 10054126 [patent_doc_number] => 09094014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'PLD architecture for flexible placement of IP function blocks' [patent_app_type] => utility [patent_app_number] => 14/243641 [patent_app_country] => US [patent_app_date] => 2014-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243641 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/243641
PLD architecture for flexible placement of IP function blocks Apr 1, 2014 Issued
Array ( [id] => 11877054 [patent_doc_number] => 09748839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Digital voltage regulator controller with multiple configurations' [patent_app_type] => utility [patent_app_number] => 14/230943 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4733 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230943 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230943
Digital voltage regulator controller with multiple configurations Mar 30, 2014 Issued
Array ( [id] => 9926481 [patent_doc_number] => 08984468 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-17 [patent_title] => 'Method to adaptively calculate resistor mesh in IC designs' [patent_app_type] => utility [patent_app_number] => 14/230981 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230981 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230981
Method to adaptively calculate resistor mesh in IC designs Mar 30, 2014 Issued
Array ( [id] => 9954528 [patent_doc_number] => 09003342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-07 [patent_title] => 'Lumped aggressor model for signal integrity timing analysis' [patent_app_type] => utility [patent_app_number] => 14/230931 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3265 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230931 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230931
Lumped aggressor model for signal integrity timing analysis Mar 30, 2014 Issued
Array ( [id] => 10010594 [patent_doc_number] => 09054120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Semiconductor device, semiconductor device design method, semiconductor device design apparatus, and program' [patent_app_type] => utility [patent_app_number] => 14/229090 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11332 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229090 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229090
Semiconductor device, semiconductor device design method, semiconductor device design apparatus, and program Mar 27, 2014 Issued
Array ( [id] => 10385207 [patent_doc_number] => 20150270214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'METHOD FOR LAYOUT DESIGN AND STRUCTURE WITH INTER-LAYER VIAS' [patent_app_type] => utility [patent_app_number] => 14/220751 [patent_app_country] => US [patent_app_date] => 2014-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14220751 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/220751
Method for layout design and structure with inter-layer vias Mar 19, 2014 Issued
Array ( [id] => 9754439 [patent_doc_number] => 20140285140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'WIRELESS POWER TRANSMISSION SYSTEM, FURNITURE HAVING WIRELESS CHARGING FUNCTION USED THEREIN, AND WIRELESS POWER TRANSMSSION APPARATUS USED THEREIN' [patent_app_type] => utility [patent_app_number] => 14/218112 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5795 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218112 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/218112
Wireless power transmission system, furniture having wireless charging function used therein, and wireless power transmission apparatus used therein Mar 17, 2014 Issued
Array ( [id] => 9906372 [patent_doc_number] => 20150061572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'BATTERY PACK, APPARATUS HAVING THE SAME AND METHOD OF CONTROLLING BATTERY' [patent_app_type] => utility [patent_app_number] => 14/217761 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6274 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217761 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/217761
Battery pack, apparatus having the same and method of controlling battery Mar 17, 2014 Issued
Array ( [id] => 11208429 [patent_doc_number] => 09438064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'System and method for alignment and compatibility detection for a wireless power transfer system' [patent_app_type] => utility [patent_app_number] => 14/218246 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 17012 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218246 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/218246
System and method for alignment and compatibility detection for a wireless power transfer system Mar 17, 2014 Issued
Array ( [id] => 11221924 [patent_doc_number] => 09450274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Method and apparatus for creating a dynamically reconfigurable energy storage device' [patent_app_type] => utility [patent_app_number] => 14/216436 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 20715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14216436 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/216436
Method and apparatus for creating a dynamically reconfigurable energy storage device Mar 16, 2014 Issued
Array ( [id] => 9600861 [patent_doc_number] => 20140197543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect' [patent_app_type] => utility [patent_app_number] => 14/216891 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10275 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14216891 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/216891
Enforcement of semiconductor structure regularity for localized transistors and interconnect Mar 16, 2014 Issued
Array ( [id] => 10245400 [patent_doc_number] => 20150130395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'Graphene-in-structure electrical energy storage' [patent_app_type] => utility [patent_app_number] => 14/215025 [patent_app_country] => US [patent_app_date] => 2014-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14215025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/215025
Graphene-in-structure electrical energy storage Mar 15, 2014 Abandoned
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