Jeffrey Kushan

Array ( [id] => 4141401 [patent_doc_number] => 06030854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method for producing a multilayer interconnection structure' [patent_app_type] => 1 [patent_app_number] => 9/111268 [patent_app_country] => US [patent_app_date] => 1998-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2602 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030854.pdf [firstpage_image] =>[orig_patent_app_number] => 111268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3945222 [patent_doc_number] => 05953603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method for manufacturing BiCMOS' [patent_app_type] => 1 [patent_app_number] => 9/103828 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3407 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953603.pdf [firstpage_image] =>[orig_patent_app_number] => 103828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4029603 [patent_doc_number] => 05994193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of making high performance MOSFET with integrated poly/metal gate electrode' [patent_app_type] => 1 [patent_app_number] => 9/095088 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4238 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994193.pdf [firstpage_image] =>[orig_patent_app_number] => 095088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3943839 [patent_doc_number] => 05998238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/093059 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 59 [patent_no_of_words] => 24040 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998238.pdf [firstpage_image] =>[orig_patent_app_number] => 093059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4070647 [patent_doc_number] => 05970357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method and structure for manufacturing high-resistance polysilicon loads in a semiconductor process' [patent_app_type] => 1 [patent_app_number] => 9/081299 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 1528 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970357.pdf [firstpage_image] =>[orig_patent_app_number] => 081299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3953151 [patent_doc_number] => 05998852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Geometrical control of device corner threshold' [patent_app_type] => 1 [patent_app_number] => 9/078517 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 5611 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998852.pdf [firstpage_image] =>[orig_patent_app_number] => 078517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4099639 [patent_doc_number] => 06066515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Multilevel leadframe for a packaged integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/072889 [patent_app_country] => US [patent_app_date] => 1998-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4333 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066515.pdf [firstpage_image] =>[orig_patent_app_number] => 072889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4154611 [patent_doc_number] => 06103603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method of fabricating gate electrodes of twin-well CMOS device' [patent_app_type] => 1 [patent_app_number] => 9/065487 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2943 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103603.pdf [firstpage_image] =>[orig_patent_app_number] => 065487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4243678 [patent_doc_number] => 06080999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Photosensitive semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/064039 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1924 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080999.pdf [firstpage_image] =>[orig_patent_app_number] => 064039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4253461 [patent_doc_number] => 06137163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor substrate and stackable semiconductor package and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/060707 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2163 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137163.pdf [firstpage_image] =>[orig_patent_app_number] => 060707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4064068 [patent_doc_number] => 06008102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of forming a three-dimensional integrated inductor' [patent_app_type] => 1 [patent_app_number] => 9/056967 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 2593 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008102.pdf [firstpage_image] =>[orig_patent_app_number] => 056967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161884 [patent_doc_number] => 06104091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Semiconductor package and the manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/053988 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3926 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104091.pdf [firstpage_image] =>[orig_patent_app_number] => 053988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4081072 [patent_doc_number] => 06054372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Stress-free silicon wafer and a die or chip made therefrom' [patent_app_type] => 1 [patent_app_number] => 9/048928 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3007 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054372.pdf [firstpage_image] =>[orig_patent_app_number] => 048928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4029632 [patent_doc_number] => 05994196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Methods of forming bipolar junction transistors using simultaneous base and emitter diffusion techniques' [patent_app_type] => 1 [patent_app_number] => 9/047099 [patent_app_country] => US [patent_app_date] => 1998-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 4971 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994196.pdf [firstpage_image] =>[orig_patent_app_number] => 047099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3996671 [patent_doc_number] => 05911104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Integrated circuit combining high frequency bipolar and high power CMOS transistors' [patent_app_type] => 1 [patent_app_number] => 9/027369 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 5848 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911104.pdf [firstpage_image] =>[orig_patent_app_number] => 027369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3947675 [patent_doc_number] => 05982022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Angled implant to improve high current operation of transistors' [patent_app_type] => 1 [patent_app_number] => 9/024287 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 1941 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982022.pdf [firstpage_image] =>[orig_patent_app_number] => 024287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4102580 [patent_doc_number] => 06051482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method for manufacturing buried-channel PMOS' [patent_app_type] => 1 [patent_app_number] => 9/024347 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2980 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051482.pdf [firstpage_image] =>[orig_patent_app_number] => 024347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4206340 [patent_doc_number] => 06027956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Process for producing planar dielectrically isolated high speed pin photodiode' [patent_app_type] => 1 [patent_app_number] => 9/019079 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 3850 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027956.pdf [firstpage_image] =>[orig_patent_app_number] => 019079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4223035 [patent_doc_number] => 06087716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Semiconductor device package having a connection substrate with turned back leads and method thereof' [patent_app_type] => 1 [patent_app_number] => 9/015079 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5258 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087716.pdf [firstpage_image] =>[orig_patent_app_number] => 015079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4102701 [patent_doc_number] => 06051488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Methods of forming semiconductor switching devices having trench-gate electrodes' [patent_app_type] => 1 [patent_app_number] => 9/007878 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2358 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051488.pdf [firstpage_image] =>[orig_patent_app_number] => 007878 [rel_patent_id] =>[rel_patent_doc_number] =>)