Search

Jeffrey Kushan

Examiner (ID: 14962)

Most Active Art Unit
1806
Art Unit(s)
1806, 1503, 1802, 1803
Total Applications
165
Issued Applications
107
Pending Applications
0
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4067748 [patent_doc_number] => 05895954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Field effect transistor with impurity concentration peak under gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/917929 [patent_app_country] => US [patent_app_date] => 1997-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4898 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895954.pdf [firstpage_image] =>[orig_patent_app_number] => 917929 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917929
Field effect transistor with impurity concentration peak under gate electrode Aug 26, 1997 Issued
Array ( [id] => 4056425 [patent_doc_number] => 05969417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Chip package device mountable on a mother board in whichever of facedown and wire bonding manners' [patent_app_type] => 1 [patent_app_number] => 8/917365 [patent_app_country] => US [patent_app_date] => 1997-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 5213 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969417.pdf [firstpage_image] =>[orig_patent_app_number] => 917365 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917365
Chip package device mountable on a mother board in whichever of facedown and wire bonding manners Aug 25, 1997 Issued
Array ( [id] => 4129942 [patent_doc_number] => 06033947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Driving circuit for electronic semiconductor devices including at least a power transistor' [patent_app_type] => 1 [patent_app_number] => 8/929349 [patent_app_country] => US [patent_app_date] => 1997-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3744 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033947.pdf [firstpage_image] =>[orig_patent_app_number] => 929349 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929349
Driving circuit for electronic semiconductor devices including at least a power transistor Aug 24, 1997 Issued
Array ( [id] => 4018634 [patent_doc_number] => 05993493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of manufacturing mirror-polished silicon wafers, and apparatus for processing silicon wafers' [patent_app_type] => 1 [patent_app_number] => 8/910396 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4574 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/993/05993493.pdf [firstpage_image] =>[orig_patent_app_number] => 910396 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910396
Method of manufacturing mirror-polished silicon wafers, and apparatus for processing silicon wafers Aug 12, 1997 Issued
Array ( [id] => 4097457 [patent_doc_number] => 06048743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Using a submicron level dimension reference' [patent_app_type] => 1 [patent_app_number] => 8/906880 [patent_app_country] => US [patent_app_date] => 1997-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2428 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048743.pdf [firstpage_image] =>[orig_patent_app_number] => 906880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906880
Using a submicron level dimension reference Aug 5, 1997 Issued
Array ( [id] => 4057079 [patent_doc_number] => 05863835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Methods of forming electrical interconnects on semiconductor substrates' [patent_app_type] => 1 [patent_app_number] => 8/906718 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1502 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/863/05863835.pdf [firstpage_image] =>[orig_patent_app_number] => 906718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906718
Methods of forming electrical interconnects on semiconductor substrates Aug 4, 1997 Issued
Array ( [id] => 3916781 [patent_doc_number] => 05951720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'IC mounting/demounting system and mounting/demounting head therefor' [patent_app_type] => 1 [patent_app_number] => 8/898841 [patent_app_country] => US [patent_app_date] => 1997-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 6248 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951720.pdf [firstpage_image] =>[orig_patent_app_number] => 898841 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/898841
IC mounting/demounting system and mounting/demounting head therefor Jul 22, 1997 Issued
08/893728 ENHANCED UNDERFILL ADHESION INCLUDING STRESS REDUCING LAYER Jul 10, 1997 Abandoned
Array ( [id] => 3966924 [patent_doc_number] => 05956583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method for forming complementary wells and self-aligned trench with a single mask' [patent_app_type] => 1 [patent_app_number] => 8/885707 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 1731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956583.pdf [firstpage_image] =>[orig_patent_app_number] => 885707 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885707
Method for forming complementary wells and self-aligned trench with a single mask Jun 29, 1997 Issued
Array ( [id] => 4163446 [patent_doc_number] => 06114755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Semiconductor package including chip housing, encapsulation and the manufacturing method' [patent_app_type] => 1 [patent_app_number] => 8/862396 [patent_app_country] => US [patent_app_date] => 1997-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3925 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114755.pdf [firstpage_image] =>[orig_patent_app_number] => 862396 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862396
Semiconductor package including chip housing, encapsulation and the manufacturing method May 22, 1997 Issued
Array ( [id] => 3952545 [patent_doc_number] => 05940680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method for manufacturing known good die array having solder bumps' [patent_app_type] => 1 [patent_app_number] => 8/854587 [patent_app_country] => US [patent_app_date] => 1997-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1676 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940680.pdf [firstpage_image] =>[orig_patent_app_number] => 854587 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/854587
Method for manufacturing known good die array having solder bumps May 11, 1997 Issued
Array ( [id] => 4103043 [patent_doc_number] => 06051512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Apparatus and method for rapid thermal processing (RTP) of a plurality of semiconductor wafers' [patent_app_type] => 1 [patent_app_number] => 8/838627 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2574 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051512.pdf [firstpage_image] =>[orig_patent_app_number] => 838627 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838627
Apparatus and method for rapid thermal processing (RTP) of a plurality of semiconductor wafers Apr 10, 1997 Issued
Array ( [id] => 4239389 [patent_doc_number] => 06075287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Integrated, multi-chip, thermally conductive packaging device and methodology' [patent_app_type] => 1 [patent_app_number] => 8/826572 [patent_app_country] => US [patent_app_date] => 1997-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4087 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075287.pdf [firstpage_image] =>[orig_patent_app_number] => 826572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826572
Integrated, multi-chip, thermally conductive packaging device and methodology Apr 2, 1997 Issued
Array ( [id] => 4065072 [patent_doc_number] => 06068668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Process for forming a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/829297 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2716 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/068/06068668.pdf [firstpage_image] =>[orig_patent_app_number] => 829297 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829297
Process for forming a semiconductor device Mar 30, 1997 Issued
Array ( [id] => 4130551 [patent_doc_number] => 06146917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Fabrication method for encapsulated micromachined structures' [patent_app_type] => 1 [patent_app_number] => 8/810387 [patent_app_country] => US [patent_app_date] => 1997-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 4754 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146917.pdf [firstpage_image] =>[orig_patent_app_number] => 810387 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/810387
Fabrication method for encapsulated micromachined structures Mar 2, 1997 Issued
Array ( [id] => 3932222 [patent_doc_number] => 05976199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Single semiconductor wafer transfer method and manufacturing system' [patent_app_type] => 1 [patent_app_number] => 8/800777 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 7826 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976199.pdf [firstpage_image] =>[orig_patent_app_number] => 800777 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/800777
Single semiconductor wafer transfer method and manufacturing system Feb 13, 1997 Issued
Array ( [id] => 4177368 [patent_doc_number] => 06037193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity' [patent_app_type] => 1 [patent_app_number] => 8/792073 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2666 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037193.pdf [firstpage_image] =>[orig_patent_app_number] => 792073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792073
Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity Jan 30, 1997 Issued
Array ( [id] => 3945011 [patent_doc_number] => 05953588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Stackable layers containing encapsulated IC chips' [patent_app_type] => 1 [patent_app_number] => 8/777747 [patent_app_country] => US [patent_app_date] => 1996-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4138 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953588.pdf [firstpage_image] =>[orig_patent_app_number] => 777747 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777747
Stackable layers containing encapsulated IC chips Dec 20, 1996 Issued
Array ( [id] => 3957726 [patent_doc_number] => 05930653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method of manufacturing a semiconductor device for surface mounting suitable for comparatively high voltages, and such a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/762515 [patent_app_country] => US [patent_app_date] => 1996-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3937 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930653.pdf [firstpage_image] =>[orig_patent_app_number] => 762515 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/762515
Method of manufacturing a semiconductor device for surface mounting suitable for comparatively high voltages, and such a semiconductor device Dec 9, 1996 Issued
Array ( [id] => 4222555 [patent_doc_number] => 06111308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Ground plane for plastic encapsulated integrated circuit die packages' [patent_app_type] => 1 [patent_app_number] => 8/686979 [patent_app_country] => US [patent_app_date] => 1996-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2553 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111308.pdf [firstpage_image] =>[orig_patent_app_number] => 686979 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/686979
Ground plane for plastic encapsulated integrated circuit die packages Jul 24, 1996 Issued
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