Search

John M Petruncio

Examiner (ID: 7674)

Most Active Art Unit
1751
Art Unit(s)
1751
Total Applications
394
Issued Applications
318
Pending Applications
23
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14177821 [patent_doc_number] => 10262931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Lateral vias for connections to buried microconductors and methods thereof [patent_app_type] => utility [patent_app_number] => 15/980546 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 12423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980546
Lateral vias for connections to buried microconductors and methods thereof May 14, 2018 Issued
Array ( [id] => 15375713 [patent_doc_number] => 10529584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => In-situ selective deposition and etching for advanced patterning applications [patent_app_type] => utility [patent_app_number] => 15/980274 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980274
In-situ selective deposition and etching for advanced patterning applications May 14, 2018 Issued
Array ( [id] => 15315671 [patent_doc_number] => 10522552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Method of fabricating vertical transistor device [patent_app_type] => utility [patent_app_number] => 15/980604 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6207 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980604 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980604
Method of fabricating vertical transistor device May 14, 2018 Issued
Array ( [id] => 14397983 [patent_doc_number] => 10312284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Semiconductor device and semiconductor device manufacturing method [patent_app_type] => utility [patent_app_number] => 15/961919 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 5852 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15961919 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/961919
Semiconductor device and semiconductor device manufacturing method Apr 24, 2018 Issued
Array ( [id] => 13360093 [patent_doc_number] => 20180231586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => NON-CONTACT TYPE VOLTAGE SENSOR FOR DUAL-WIRE POWER CABLE AND METHOD FOR COMPENSATING INSTALLATION POSITION VARIATION THEREOF [patent_app_type] => utility [patent_app_number] => 15/952924 [patent_app_country] => US [patent_app_date] => 2018-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15952924 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/952924
Non-contact type voltage sensor for dual-wire power cable and method for compensating installation position variation thereof Apr 12, 2018 Issued
Array ( [id] => 13378497 [patent_doc_number] => 20180240790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => Method and Structure for Semiconductor Mid-End-Of-Line (MEOL) Process [patent_app_type] => utility [patent_app_number] => 15/952316 [patent_app_country] => US [patent_app_date] => 2018-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15952316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/952316
Method and structure for semiconductor mid-end-of-line (MEOL) process Apr 12, 2018 Issued
Array ( [id] => 16988058 [patent_doc_number] => 11075241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Solid-state imaging device and electronic apparatus [patent_app_type] => utility [patent_app_number] => 16/496730 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 13301 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16496730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/496730
Solid-state imaging device and electronic apparatus Mar 15, 2018 Issued
Array ( [id] => 15356197 [patent_doc_number] => 10526703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Film formation apparatus for forming semiconductor structure having shower head with plural hole patterns and with corresponding different plural hole densities [patent_app_type] => utility [patent_app_number] => 15/922250 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922250 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922250
Film formation apparatus for forming semiconductor structure having shower head with plural hole patterns and with corresponding different plural hole densities Mar 14, 2018 Issued
Array ( [id] => 15170477 [patent_doc_number] => 10490745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Vertical and planar RRAM with tip electrodes and methods for producing the same [patent_app_type] => utility [patent_app_number] => 15/921293 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 43 [patent_no_of_words] => 6063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15921293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/921293
Vertical and planar RRAM with tip electrodes and methods for producing the same Mar 13, 2018 Issued
Array ( [id] => 14491895 [patent_doc_number] => 10332746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Post UV cure for gapfill improvement [patent_app_type] => utility [patent_app_number] => 15/920753 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920753 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920753
Post UV cure for gapfill improvement Mar 13, 2018 Issued
Array ( [id] => 14875121 [patent_doc_number] => 20190287802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => MASK FORMATION BY SELECTIVELY REMOVING PORTIONS OF A LAYER THAT HAVE NOT BEEN IMPLANTED [patent_app_type] => utility [patent_app_number] => 15/920745 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920745 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920745
Mask formation by selectively removing portions of a layer that have not been implanted Mar 13, 2018 Issued
Array ( [id] => 15606729 [patent_doc_number] => 10584414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Substrate processing method that includes step of introducing ballast gas to exhaust line while supplying processing gas [patent_app_type] => utility [patent_app_number] => 15/921506 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9570 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15921506 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/921506
Substrate processing method that includes step of introducing ballast gas to exhaust line while supplying processing gas Mar 13, 2018 Issued
Array ( [id] => 14769077 [patent_doc_number] => 10395940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-27 [patent_title] => Method of etching microelectronic mechanical system features in a silicon wafer [patent_app_type] => utility [patent_app_number] => 15/919889 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9491 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919889 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919889
Method of etching microelectronic mechanical system features in a silicon wafer Mar 12, 2018 Issued
Array ( [id] => 14397719 [patent_doc_number] => 10312150 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-04 [patent_title] => Protected trench isolation for fin-type field-effect transistors [patent_app_type] => utility [patent_app_number] => 15/919594 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919594 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919594
Protected trench isolation for fin-type field-effect transistors Mar 12, 2018 Issued
Array ( [id] => 16433134 [patent_doc_number] => 10833234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Optoelectronic semiconductor component [patent_app_type] => utility [patent_app_number] => 16/480966 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3837 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16480966 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/480966
Optoelectronic semiconductor component Mar 4, 2018 Issued
Array ( [id] => 12884359 [patent_doc_number] => 20180186628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ULTRASONIC TRANSDUCERS AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/910776 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910776 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910776
Complementary metal oxide semiconductor (CMOS) ultrasonic transducers and methods for forming the same Mar 1, 2018 Issued
Array ( [id] => 16746661 [patent_doc_number] => 10971666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Method for manufacturing an optical module and optical module [patent_app_type] => utility [patent_app_number] => 16/484189 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7185 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16484189 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/484189
Method for manufacturing an optical module and optical module Feb 27, 2018 Issued
Array ( [id] => 15308691 [patent_doc_number] => 10519035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-31 [patent_title] => Covalent chemical surface modification of surfaces with available silicon or nitrogen [patent_app_type] => utility [patent_app_number] => 15/900762 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 38 [patent_no_of_words] => 5351 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900762
Covalent chemical surface modification of surfaces with available silicon or nitrogen Feb 19, 2018 Issued
Array ( [id] => 16434742 [patent_doc_number] => 10834854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Methods for the manufacture of thermal interfaces, thermal interfaces, and articles comprising the same [patent_app_type] => utility [patent_app_number] => 15/894175 [patent_app_country] => US [patent_app_date] => 2018-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 12125 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15894175 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/894175
Methods for the manufacture of thermal interfaces, thermal interfaces, and articles comprising the same Feb 11, 2018 Issued
Array ( [id] => 15332475 [patent_doc_number] => 20200006567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/484148 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 45909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16484148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/484148
SEMICONDUCTOR DEVICE Feb 6, 2018 Abandoned
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