Search

John M Petruncio

Examiner (ID: 7674)

Most Active Art Unit
1751
Art Unit(s)
1751
Total Applications
394
Issued Applications
318
Pending Applications
23
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15792075 [patent_doc_number] => 10629770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Semiconductor method having annealing of epitaxially grown layers to form semiconductor structure with low dislocation density [patent_app_type] => utility [patent_app_number] => 16/022856 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 15408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022856 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022856
Semiconductor method having annealing of epitaxially grown layers to form semiconductor structure with low dislocation density Jun 28, 2018 Issued
Array ( [id] => 15427931 [patent_doc_number] => 10546905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Method for manufacturing array substrate and method for manufacturing display device [patent_app_type] => utility [patent_app_number] => 16/023400 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2870 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16023400 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/023400
Method for manufacturing array substrate and method for manufacturing display device Jun 28, 2018 Issued
Array ( [id] => 15332205 [patent_doc_number] => 20200006432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => METHODS AND APPARATUS FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/021804 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021804 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/021804
Methods and apparatus for three-dimensional non-volatile memory Jun 27, 2018 Issued
Array ( [id] => 15703975 [patent_doc_number] => 10608175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Resistance change device having electrode disposed between resistance switching layer and ferroelectric layer [patent_app_type] => utility [patent_app_number] => 16/016550 [patent_app_country] => US [patent_app_date] => 2018-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16016550 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/016550
Resistance change device having electrode disposed between resistance switching layer and ferroelectric layer Jun 22, 2018 Issued
Array ( [id] => 15300261 [patent_doc_number] => 20190393266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => VERTICAL ARRAY OF RESISTIVE SWITCHING DEVICES HAVING A TUNABLE OXYGEN VACANCY CONCENTRATION [patent_app_type] => utility [patent_app_number] => 16/015934 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16015934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/015934
Vertical array of resistive switching devices having a tunable oxygen vacancy concentration Jun 21, 2018 Issued
Array ( [id] => 14317865 [patent_doc_number] => 20190148636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => CROSS-POINT ARRAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/013962 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013962 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/013962
Cross-point array device and method of manufacturing the same Jun 20, 2018 Issued
Array ( [id] => 15641725 [patent_doc_number] => 10593875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Self-aligned 3D memory with confined cell [patent_app_type] => utility [patent_app_number] => 16/009901 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 48 [patent_no_of_words] => 7628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16009901 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/009901
Self-aligned 3D memory with confined cell Jun 14, 2018 Issued
Array ( [id] => 16716077 [patent_doc_number] => 20210083224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => ENCAPSULATION FILM [patent_app_type] => utility [patent_app_number] => 16/620448 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16620448 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/620448
Encapsulation film Jun 10, 2018 Issued
Array ( [id] => 13667837 [patent_doc_number] => 10164100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Formation method and structure semiconductor device with source/drain structures [patent_app_type] => utility [patent_app_number] => 16/004727 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004727
Formation method and structure semiconductor device with source/drain structures Jun 10, 2018 Issued
Array ( [id] => 13589891 [patent_doc_number] => 20180346494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => NOVEL CHLOROSILYLARYLGERMANES, METHOD FOR PREPARATION THEREOF AND USE THEREOF [patent_app_type] => utility [patent_app_number] => 15/994110 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994110 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994110
Chlorosilylarylgermanes, method for preparation thereof and use thereof May 30, 2018 Issued
Array ( [id] => 13832479 [patent_doc_number] => 20190019724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => CYCLIC CONFORMAL DEPOSITION/ANNEAL/ETCH FOR SI GAPFILL [patent_app_type] => utility [patent_app_number] => 15/991376 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991376
Cyclic conformal deposition/anneal/etch for Si gapfill May 28, 2018 Issued
Array ( [id] => 14671813 [patent_doc_number] => 10373825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-06 [patent_title] => Method for manufacturing gallium nitride substrate using core-shell nanoparticle [patent_app_type] => utility [patent_app_number] => 15/991464 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 7873 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991464
Method for manufacturing gallium nitride substrate using core-shell nanoparticle May 28, 2018 Issued
Array ( [id] => 15217821 [patent_doc_number] => 20190371597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => METHOD FOR MANUFACTURING GALLIUM NITRIDE SUBSTRATE USING THE HYDRIDE VAPOR PHASE EPITAXY [patent_app_type] => utility [patent_app_number] => 15/991481 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991481 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991481
Method for manufacturing gallium nitride substrate using the hydride vapor phase epitaxy May 28, 2018 Issued
Array ( [id] => 13847755 [patent_doc_number] => 20190027362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => PRE-TREATMENT APPROACH TO IMPROVE CONTINUITY OF ULTRA-THIN AMORPHOUS SILICON FILM ON SILICON OXIDE [patent_app_type] => utility [patent_app_number] => 15/988771 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988771
Pre-treatment approach to improve continuity of ultra-thin amorphous silicon film on silicon oxide May 23, 2018 Issued
Array ( [id] => 15200715 [patent_doc_number] => 10497864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Resistance change memory devices [patent_app_type] => utility [patent_app_number] => 15/986968 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15986968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/986968
Resistance change memory devices May 22, 2018 Issued
Array ( [id] => 14781277 [patent_doc_number] => 20190265536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Array Substrate and Manufacturing Method Thereof, and Display Device [patent_app_type] => utility [patent_app_number] => 16/335995 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16335995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/335995
Array substrate and manufacturing method thereof, and display device May 22, 2018 Issued
Array ( [id] => 13799321 [patent_doc_number] => 20190013199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => METHODS FOR FORMING A SILICON GERMANIUM TIN LAYER AND RELATED SEMICONDUCTOR DEVICE STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/985261 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15985261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/985261
Methods for forming a silicon germanium tin layer and related semiconductor device structures May 20, 2018 Issued
Array ( [id] => 15519491 [patent_doc_number] => 10566344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Method of manufacturing semiconductor device using exposure mask having light transmission holes to transfer slit shaped pattern to stack structure [patent_app_type] => utility [patent_app_number] => 15/983726 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 11404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983726 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/983726
Method of manufacturing semiconductor device using exposure mask having light transmission holes to transfer slit shaped pattern to stack structure May 17, 2018 Issued
Array ( [id] => 14644433 [patent_doc_number] => 10366966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-30 [patent_title] => Method of manufacturing integrated fan-out package [patent_app_type] => utility [patent_app_number] => 15/981929 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 7596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981929 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981929
Method of manufacturing integrated fan-out package May 16, 2018 Issued
Array ( [id] => 13571409 [patent_doc_number] => 20180337252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => FORMING OF A MOS TRANSISTOR BASED ON A TWO-DIMENSIONAL SEMICONDUCTOR MATERIAL [patent_app_type] => utility [patent_app_number] => 15/981953 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981953 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981953
Forming of a MOS transistor based on a two-dimensional semiconductor material May 16, 2018 Issued
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