Kevin E Weddington

Array ( [id] => 4258337 [patent_doc_number] => 06145105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method and apparatus for scan testing digital circuits' [patent_app_type] => 1 [patent_app_number] => 9/192839 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 3789 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145105.pdf [firstpage_image] =>[orig_patent_app_number] => 192839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110970 [patent_doc_number] => 06134693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Automatic repeat request communication system with improved throughput by using reception confirmation table' [patent_app_type] => 1 [patent_app_number] => 9/014589 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11342 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134693.pdf [firstpage_image] =>[orig_patent_app_number] => 014589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4200629 [patent_doc_number] => 06021514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Limited latch linehold capability for LBIST testing' [patent_app_type] => 1 [patent_app_number] => 9/012047 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1622 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021514.pdf [firstpage_image] =>[orig_patent_app_number] => 012047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4177891 [patent_doc_number] => 06105155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method and apparatus for performing on-chip function checks and locating detected anomalies within a nested time interval using CRCs or the like' [patent_app_type] => 1 [patent_app_number] => 9/010726 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 5472 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105155.pdf [firstpage_image] =>[orig_patent_app_number] => 010726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4127415 [patent_doc_number] => 06058500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'High-speed syndrome calculation' [patent_app_type] => 1 [patent_app_number] => 9/009480 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9504 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058500.pdf [firstpage_image] =>[orig_patent_app_number] => 009480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4089207 [patent_doc_number] => 06070259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Dynamic logic element having non-invasive scan chain insertion' [patent_app_type] => 1 [patent_app_number] => 9/007407 [patent_app_country] => US [patent_app_date] => 1998-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 3 [patent_no_of_words] => 4563 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070259.pdf [firstpage_image] =>[orig_patent_app_number] => 007407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257764 [patent_doc_number] => 06081920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method and apparatus for fast decoding of a Reed-Solomon code' [patent_app_type] => 1 [patent_app_number] => 9/004748 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3501 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081920.pdf [firstpage_image] =>[orig_patent_app_number] => 004748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257714 [patent_doc_number] => 06081918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Loss resilient code with cascading series of redundant layers' [patent_app_type] => 1 [patent_app_number] => 8/965604 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 14266 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081918.pdf [firstpage_image] =>[orig_patent_app_number] => 965604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3971721 [patent_doc_number] => 06000054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method and apparatus for encoding and decoding binary information using restricted coded modulation and parallel concatenated convolution codes' [patent_app_type] => 1 [patent_app_number] => 8/963493 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6839 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000054.pdf [firstpage_image] =>[orig_patent_app_number] => 963493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237028 [patent_doc_number] => 06041430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Error detection and correction code for data and check code fields' [patent_app_type] => 1 [patent_app_number] => 8/963501 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 7 [patent_no_of_words] => 2861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041430.pdf [firstpage_image] =>[orig_patent_app_number] => 963501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3974358 [patent_doc_number] => 05978947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Built-in self-test in a plurality of stages controlled by a token passing network and method' [patent_app_type] => 1 [patent_app_number] => 8/944617 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 15818 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978947.pdf [firstpage_image] =>[orig_patent_app_number] => 944617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202885 [patent_doc_number] => 06094739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Trellis decoder for real-time video rate decoding and de-interleaving' [patent_app_type] => 1 [patent_app_number] => 8/936316 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4391 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094739.pdf [firstpage_image] =>[orig_patent_app_number] => 936316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139607 [patent_doc_number] => 06073267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Semiconductor integrated circuit with error detecting circuit' [patent_app_type] => 1 [patent_app_number] => 8/937657 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7260 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073267.pdf [firstpage_image] =>[orig_patent_app_number] => 937657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237043 [patent_doc_number] => 06041431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method and apparatus for performing error correction code operations' [patent_app_type] => 1 [patent_app_number] => 8/933568 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 13704 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041431.pdf [firstpage_image] =>[orig_patent_app_number] => 933568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4255917 [patent_doc_number] => 06119262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method and apparatus for solving key equation polynomials in decoding error correction codes' [patent_app_type] => 1 [patent_app_number] => 8/914427 [patent_app_country] => US [patent_app_date] => 1997-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4344 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119262.pdf [firstpage_image] =>[orig_patent_app_number] => 914427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4226321 [patent_doc_number] => 06029266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Error correcting apparatus and method of digital processing system for correcting general and erasure errors' [patent_app_type] => 1 [patent_app_number] => 8/906933 [patent_app_country] => US [patent_app_date] => 1997-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4002 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029266.pdf [firstpage_image] =>[orig_patent_app_number] => 906933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970398 [patent_doc_number] => 05958058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'User-selectable power management interface with application threshold warnings' [patent_app_type] => 1 [patent_app_number] => 8/896413 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5128 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958058.pdf [firstpage_image] =>[orig_patent_app_number] => 896413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4236068 [patent_doc_number] => 06041365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Apparatus and method for high performance remote application gateway servers' [patent_app_type] => 1 [patent_app_number] => 8/885141 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13067 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041365.pdf [firstpage_image] =>[orig_patent_app_number] => 885141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969253 [patent_doc_number] => 05948106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'System for thermal overload detection and prevention for an integrated circuit processor' [patent_app_type] => 1 [patent_app_number] => 8/882613 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8263 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948106.pdf [firstpage_image] =>[orig_patent_app_number] => 882613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152694 [patent_doc_number] => 06035436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method and apparatus for fault on use data error handling' [patent_app_type] => 1 [patent_app_number] => 8/882595 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2257 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035436.pdf [firstpage_image] =>[orig_patent_app_number] => 882595 [rel_patent_id] =>[rel_patent_doc_number] =>)