Kyle J Moody
Examiner (ID: 11195, Phone: (571)272-5242 , Office: P/2838 )
Most Active Art Unit | 2838 |
Art Unit(s) | 2838 |
Total Applications | 738 |
Issued Applications | 638 |
Pending Applications | 49 |
Abandoned Applications | 51 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6494746
[patent_doc_number] => 20020190379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-19
[patent_title] => 'W-CVD with fluorine-free tungsten nucleation'
[patent_app_type] => new
[patent_app_number] => 10/104842
[patent_app_country] => US
[patent_app_date] => 2002-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2406
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[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0190/20020190379.pdf
[firstpage_image] =>[orig_patent_app_number] => 10104842
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/104842 | W-CVD with fluorine-free tungsten nucleation | Mar 21, 2002 | Abandoned |
Array
(
[id] => 5900952
[patent_doc_number] => 20020140007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/100061
[patent_app_country] => US
[patent_app_date] => 2002-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3332
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20020140007.pdf
[firstpage_image] =>[orig_patent_app_number] => 10100061
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/100061 | Method of fabricating an air bridge | Mar 18, 2002 | Issued |
Array
(
[id] => 5903319
[patent_doc_number] => 20020141141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Solid electrolytic multilayer capacitor'
[patent_app_type] => new
[patent_app_number] => 10/095447
[patent_app_country] => US
[patent_app_date] => 2002-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 9933
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[pdf_file] => publications/A1/0141/20020141141.pdf
[firstpage_image] =>[orig_patent_app_number] => 10095447
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/095447 | Solid electrolytic multilayer capacitor | Mar 12, 2002 | Issued |
Array
(
[id] => 6048223
[patent_doc_number] => 20020168849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-14
[patent_title] => 'Method of manufacturing interconnection line in semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/081661
[patent_app_country] => US
[patent_app_date] => 2002-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20020168849.pdf
[firstpage_image] =>[orig_patent_app_number] => 10081661
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/081661 | Method of manufacturing interconnection line in semiconductor device | Feb 21, 2002 | Issued |
Array
(
[id] => 6738202
[patent_doc_number] => 20030155570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-21
[patent_title] => 'Method of measuring the width of a damascene resistor'
[patent_app_type] => new
[patent_app_number] => 10/079092
[patent_app_country] => US
[patent_app_date] => 2002-02-20
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[pdf_file] => publications/A1/0155/20030155570.pdf
[firstpage_image] =>[orig_patent_app_number] => 10079092
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/079092 | Damascene resistor and method for measuring the width of same | Feb 19, 2002 | Issued |
Array
(
[id] => 1277851
[patent_doc_number] => 06645832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-11
[patent_title] => 'Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack'
[patent_app_type] => B2
[patent_app_number] => 10/077822
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[pdf_file] => patents/06/645/06645832.pdf
[firstpage_image] =>[orig_patent_app_number] => 10077822
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/077822 | Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack | Feb 19, 2002 | Issued |
Array
(
[id] => 7317933
[patent_doc_number] => 20040224501
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'MANUFACTURING METHOD FOR MAKING TUNGSTEN-PLUG IN AN INTERGRATED CIRCUIT DEVICE WITHOUT VOLCANO PHENOMENA'
[patent_app_type] => new
[patent_app_number] => 09/243433
[patent_app_country] => US
[patent_app_date] => 2002-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 2332
[patent_no_of_claims] => 12
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0224/20040224501.pdf
[firstpage_image] =>[orig_patent_app_number] => 09243433
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/243433 | MANUFACTURING METHOD FOR MAKING TUNGSTEN-PLUG IN AN INTERGRATED CIRCUIT DEVICE WITHOUT VOLCANO PHENOMENA | Feb 7, 2002 | Abandoned |
Array
(
[id] => 6523173
[patent_doc_number] => 20020109234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-15
[patent_title] => 'Semiconductor device having multi-layer copper line and method of forming the same'
[patent_app_type] => new
[patent_app_number] => 10/067342
[patent_app_country] => US
[patent_app_date] => 2002-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3289
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[pdf_file] => publications/A1/0109/20020109234.pdf
[firstpage_image] =>[orig_patent_app_number] => 10067342
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/067342 | Semiconductor device having multi-layer copper line and method of forming the same | Feb 6, 2002 | Issued |
Array
(
[id] => 6630822
[patent_doc_number] => 20020086514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-04
[patent_title] => 'Fabrication method of wiring substrate for mounting semiconductor element and semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/072351
[patent_app_country] => US
[patent_app_date] => 2002-02-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0086/20020086514.pdf
[firstpage_image] =>[orig_patent_app_number] => 10072351
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/072351 | Fabrication method of wiring substrate for mounting semiconductor element and semiconductor device | Feb 6, 2002 | Issued |
Array
(
[id] => 6851634
[patent_doc_number] => 20030143837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-31
[patent_title] => 'Method of depositing a catalytic layer'
[patent_app_type] => new
[patent_app_number] => 10/059851
[patent_app_country] => US
[patent_app_date] => 2002-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[pdf_file] => publications/A1/0143/20030143837.pdf
[firstpage_image] =>[orig_patent_app_number] => 10059851
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/059851 | Method of depositing a catalytic layer | Jan 27, 2002 | Abandoned |
Array
(
[id] => 6048219
[patent_doc_number] => 20020168845
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-14
[patent_title] => 'Semiconductor copper bond pad surface protection'
[patent_app_type] => new
[patent_app_number] => 10/051482
[patent_app_country] => US
[patent_app_date] => 2002-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => publications/A1/0168/20020168845.pdf
[firstpage_image] =>[orig_patent_app_number] => 10051482
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/051482 | Semiconductor copper bond pad surface protection | Jan 17, 2002 | Issued |
Array
(
[id] => 1299762
[patent_doc_number] => 06624060
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-23
[patent_title] => 'Method and apparatus for pretreating a substrate prior to electroplating'
[patent_app_type] => B2
[patent_app_number] => 10/045782
[patent_app_country] => US
[patent_app_date] => 2002-01-12
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[firstpage_image] =>[orig_patent_app_number] => 10045782
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/045782 | Method and apparatus for pretreating a substrate prior to electroplating | Jan 11, 2002 | Issued |
Array
(
[id] => 6287754
[patent_doc_number] => 20020054471
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-09
[patent_title] => 'Method of making a parallel capacitor laminate'
[patent_app_type] => new
[patent_app_number] => 10/043830
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10043830
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/043830 | Method of making a parallel capacitor laminate | Jan 8, 2002 | Issued |
Array
(
[id] => 6753497
[patent_doc_number] => 20030001273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-02
[patent_title] => 'Structure and method for isolating porous low-k dielectric films'
[patent_app_type] => new
[patent_app_number] => 10/038352
[patent_app_country] => US
[patent_app_date] => 2002-01-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/038352 | Structure and method for isolating porous low-k dielectric films | Jan 1, 2002 | Issued |
Array
(
[id] => 6823843
[patent_doc_number] => 20030234465
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-25
[patent_title] => 'Directional assembly of carbon nanotube strings'
[patent_app_type] => new
[patent_app_number] => 10/038102
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10038102
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/038102 | Directional assembly of carbon nanotube strings | Jan 1, 2002 | Issued |
Array
(
[id] => 1341511
[patent_doc_number] => 06586322
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-01
[patent_title] => 'Method of making a bump on a substrate using multiple photoresist layers'
[patent_app_type] => B1
[patent_app_number] => 10/032341
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10032341
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/032341 | Method of making a bump on a substrate using multiple photoresist layers | Dec 20, 2001 | Issued |
Array
(
[id] => 6635945
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[patent_title] => 'Contact structure, method of forming the same, semiconductor device, and method of manufacturing the same'
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Array
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[patent_title] => 'Method for integrating passives on-die utilizing under bump metal and related structure'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/015672 | Method for fabricating a semiconductor device | Dec 16, 2001 | Issued |
Array
(
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[patent_title] => 'Solid electrolytic capacitor and manufacturing method thereof'
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[firstpage_image] =>[orig_patent_app_number] => 09979751
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/979751 | Solid electrolytic capacitor and manufacturing method thereof | Nov 26, 2001 | Issued |