Search

Kyle J Moody

Examiner (ID: 11195, Phone: (571)272-5242 , Office: P/2838 )

Most Active Art Unit
2838
Art Unit(s)
2838
Total Applications
738
Issued Applications
638
Pending Applications
49
Abandoned Applications
51

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6306764 [patent_doc_number] => 20020094655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Electric double layer capacitor and method of forming the same' [patent_app_type] => new [patent_app_number] => 09/987923 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 16223 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094655.pdf [firstpage_image] =>[orig_patent_app_number] => 09987923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/987923
Electric double layer capacitor and method of forming the same Nov 15, 2001 Abandoned
Array ( [id] => 1303141 [patent_doc_number] => 06616713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method for fabricating chip type solid electrolytic capacitor and apparatus for performing the same method' [patent_app_type] => B2 [patent_app_number] => 09/987251 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7968 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/616/06616713.pdf [firstpage_image] =>[orig_patent_app_number] => 09987251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/987251
Method for fabricating chip type solid electrolytic capacitor and apparatus for performing the same method Nov 13, 2001 Issued
Array ( [id] => 7628813 [patent_doc_number] => 06819546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Packaged solid electrolytic capacitor and method of making the same' [patent_app_type] => B2 [patent_app_number] => 10/008934 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 157 [patent_no_of_words] => 20633 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819546.pdf [firstpage_image] =>[orig_patent_app_number] => 10008934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/008934
Packaged solid electrolytic capacitor and method of making the same Nov 8, 2001 Issued
Array ( [id] => 6618151 [patent_doc_number] => 20020064908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/986051 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5758 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20020064908.pdf [firstpage_image] =>[orig_patent_app_number] => 09986051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986051
Semiconductor device and method of manufacturing the same Nov 6, 2001 Issued
Array ( [id] => 1258398 [patent_doc_number] => 06667787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Polarizer' [patent_app_type] => B2 [patent_app_number] => 09/984514 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6322 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667787.pdf [firstpage_image] =>[orig_patent_app_number] => 09984514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/984514
Polarizer Oct 29, 2001 Issued
Array ( [id] => 6539177 [patent_doc_number] => 20020137269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method for forming raised structures by controlled selective epitaxial growth of facet using spacer' [patent_app_type] => new [patent_app_number] => 10/046497 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5246 [patent_no_of_claims] => 122 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137269.pdf [firstpage_image] =>[orig_patent_app_number] => 10046497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/046497
Method for forming raised structures by controlled selective epitaxial growth of facet using spacer Oct 25, 2001 Abandoned
Array ( [id] => 5967610 [patent_doc_number] => 20020090484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Plating bath' [patent_app_type] => new [patent_app_number] => 09/981852 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4201 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20020090484.pdf [firstpage_image] =>[orig_patent_app_number] => 09981852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/981852
Plating bath Oct 16, 2001 Abandoned
Array ( [id] => 1346466 [patent_doc_number] => 06583039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Method of forming a bump on a copper pad' [patent_app_type] => B2 [patent_app_number] => 09/978422 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 26 [patent_no_of_words] => 4945 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583039.pdf [firstpage_image] =>[orig_patent_app_number] => 09978422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978422
Method of forming a bump on a copper pad Oct 14, 2001 Issued
Array ( [id] => 1387264 [patent_doc_number] => 06555914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Integrated circuit package via' [patent_app_type] => B1 [patent_app_number] => 09/975871 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2308 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555914.pdf [firstpage_image] =>[orig_patent_app_number] => 09975871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975871
Integrated circuit package via Oct 11, 2001 Issued
Array ( [id] => 1340282 [patent_doc_number] => 06589887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Forming metal-derived layers by simultaneous deposition and evaporation of metal' [patent_app_type] => B1 [patent_app_number] => 09/975612 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5320 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/589/06589887.pdf [firstpage_image] =>[orig_patent_app_number] => 09975612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975612
Forming metal-derived layers by simultaneous deposition and evaporation of metal Oct 10, 2001 Issued
Array ( [id] => 6643492 [patent_doc_number] => 20030007316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Electric double layer capacitor and method for producing the same' [patent_app_type] => new [patent_app_number] => 09/975194 [patent_app_country] => US [patent_app_date] => 2001-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6846 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007316.pdf [firstpage_image] =>[orig_patent_app_number] => 09975194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975194
Method of producing electrical double layer capacitor and method of mounting electrical double layer capacitor on a circuit substrate Oct 9, 2001 Issued
Array ( [id] => 1257319 [patent_doc_number] => 06667536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Thin film multi-layer high Q transformer formed in a semiconductor substrate' [patent_app_type] => B2 [patent_app_number] => 09/972481 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5466 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667536.pdf [firstpage_image] =>[orig_patent_app_number] => 09972481 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972481
Thin film multi-layer high Q transformer formed in a semiconductor substrate Oct 4, 2001 Issued
Array ( [id] => 6834236 [patent_doc_number] => 20030161781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Novel carbon materials and carbon/carbon composites based on modified poly (phenylene ether) for energy production and storage devices, and methods of making them' [patent_app_type] => new [patent_app_number] => 09/968290 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10789 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20030161781.pdf [firstpage_image] =>[orig_patent_app_number] => 09968290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/968290
Novel carbon materials and carbon/carbon composites based on modified poly (phenylene ether) for energy production and storage devices, and methods of making them Sep 30, 2001 Abandoned
Array ( [id] => 6674434 [patent_doc_number] => 20030060037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method of manufacturing trench conductor line' [patent_app_type] => new [patent_app_number] => 09/967712 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20030060037.pdf [firstpage_image] =>[orig_patent_app_number] => 09967712 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/967712
Method of manufacturing trench conductor line Sep 26, 2001 Abandoned
Array ( [id] => 6617163 [patent_doc_number] => 20020016057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Fill material for dual damascene processes' [patent_app_type] => new [patent_app_number] => 09/966208 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10847 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20020016057.pdf [firstpage_image] =>[orig_patent_app_number] => 09966208 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966208
Fill material for dual damascene processes Sep 26, 2001 Abandoned
Array ( [id] => 1239703 [patent_doc_number] => 06686273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Method of fabricating copper interconnects with very low-k inter-level insulator' [patent_app_type] => B2 [patent_app_number] => 09/965582 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1969 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686273.pdf [firstpage_image] =>[orig_patent_app_number] => 09965582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965582
Method of fabricating copper interconnects with very low-k inter-level insulator Sep 25, 2001 Issued
Array ( [id] => 6409267 [patent_doc_number] => 20020182850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Interconnect structure manufacturing process' [patent_app_type] => new [patent_app_number] => 09/960982 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2283 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182850.pdf [firstpage_image] =>[orig_patent_app_number] => 09960982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/960982
Interconnect structure manufacturing process Sep 24, 2001 Abandoned
Array ( [id] => 1412569 [patent_doc_number] => 06524943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method of forming metal bumps' [patent_app_type] => B1 [patent_app_number] => 09/961351 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 5639 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524943.pdf [firstpage_image] =>[orig_patent_app_number] => 09961351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961351
Method of forming metal bumps Sep 24, 2001 Issued
Array ( [id] => 993625 [patent_doc_number] => 06916724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 09/956461 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8712 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/916/06916724.pdf [firstpage_image] =>[orig_patent_app_number] => 09956461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956461
Semiconductor device and method for manufacturing the same Sep 19, 2001 Issued
Array ( [id] => 5859345 [patent_doc_number] => 20020123219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Method of forming a via of a dual damascene with low resistance' [patent_app_type] => new [patent_app_number] => 09/682481 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1913 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20020123219.pdf [firstpage_image] =>[orig_patent_app_number] => 09682481 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/682481
Method of forming a via of a dual damascene with low resistance Sep 6, 2001 Abandoned
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