Search

Lindsay M Maguire

Examiner (ID: 2393, Phone: (571)272-6039 , Office: P/3693 )

Most Active Art Unit
3693
Art Unit(s)
3693, 3695, 3692, 3619, 3634
Total Applications
797
Issued Applications
386
Pending Applications
54
Abandoned Applications
319

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3963051 [patent_doc_number] => 05936424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'High speed bus with tree structure for selecting bus driver' [patent_app_type] => 1 [patent_app_number] => 8/950380 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 6493 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936424.pdf [firstpage_image] =>[orig_patent_app_number] => 950380 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950380
High speed bus with tree structure for selecting bus driver Oct 13, 1997 Issued
Array ( [id] => 4032357 [patent_doc_number] => 05883525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'FPGA architecture with repeatable titles including routing matrices and logic matrices' [patent_app_type] => 1 [patent_app_number] => 8/943890 [patent_app_country] => US [patent_app_date] => 1997-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 12487 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883525.pdf [firstpage_image] =>[orig_patent_app_number] => 943890 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/943890
FPGA architecture with repeatable titles including routing matrices and logic matrices Oct 2, 1997 Issued
Array ( [id] => 3991746 [patent_doc_number] => 05959467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'High speed dynamic differential logic circuit employing capacitance matching devices' [patent_app_type] => 1 [patent_app_number] => 8/938250 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4630 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959467.pdf [firstpage_image] =>[orig_patent_app_number] => 938250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938250
High speed dynamic differential logic circuit employing capacitance matching devices Sep 25, 1997 Issued
Array ( [id] => 4028803 [patent_doc_number] => 05926032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Accommodating components' [patent_app_type] => 1 [patent_app_number] => 8/928160 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 5938 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926032.pdf [firstpage_image] =>[orig_patent_app_number] => 928160 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/928160
Accommodating components Sep 11, 1997 Issued
Array ( [id] => 4229402 [patent_doc_number] => 06011411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'CMOS logic circuit with reduced circuit area' [patent_app_type] => 1 [patent_app_number] => 8/926450 [patent_app_country] => US [patent_app_date] => 1997-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 40 [patent_no_of_words] => 21837 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011411.pdf [firstpage_image] =>[orig_patent_app_number] => 926450 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/926450
CMOS logic circuit with reduced circuit area Sep 9, 1997 Issued
Array ( [id] => 4011576 [patent_doc_number] => 06005413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => '5V tolerant PCI I/O buffer on 2.5V technology' [patent_app_type] => 1 [patent_app_number] => 8/927358 [patent_app_country] => US [patent_app_date] => 1997-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7287 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005413.pdf [firstpage_image] =>[orig_patent_app_number] => 927358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927358
5V tolerant PCI I/O buffer on 2.5V technology Sep 8, 1997 Issued
Array ( [id] => 4019451 [patent_doc_number] => 05963057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Chip level bias for buffers driving voltages greater than transistor tolerance' [patent_app_type] => 1 [patent_app_number] => 8/910730 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4437 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963057.pdf [firstpage_image] =>[orig_patent_app_number] => 910730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910730
Chip level bias for buffers driving voltages greater than transistor tolerance Aug 12, 1997 Issued
Array ( [id] => 4121830 [patent_doc_number] => 06046607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Logic circuit controlled by a plurality of clock signals' [patent_app_type] => 1 [patent_app_number] => 8/911106 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4425 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046607.pdf [firstpage_image] =>[orig_patent_app_number] => 911106 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911106
Logic circuit controlled by a plurality of clock signals Aug 12, 1997 Issued
Array ( [id] => 4081928 [patent_doc_number] => 05966030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Output buffer with regulated voltage biasing for driving voltages greater than transistor tolerance' [patent_app_type] => 1 [patent_app_number] => 8/906357 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3675 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966030.pdf [firstpage_image] =>[orig_patent_app_number] => 906357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906357
Output buffer with regulated voltage biasing for driving voltages greater than transistor tolerance Aug 4, 1997 Issued
Array ( [id] => 4214041 [patent_doc_number] => 06028449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Integrated circuit I/O buffer having pull-up to voltages greater than transistor tolerance' [patent_app_type] => 1 [patent_app_number] => 8/906343 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4037 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028449.pdf [firstpage_image] =>[orig_patent_app_number] => 906343 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906343
Integrated circuit I/O buffer having pull-up to voltages greater than transistor tolerance Aug 4, 1997 Issued
Array ( [id] => 3881517 [patent_doc_number] => 05764085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus for sharing a fet between a plurality of operationally exclusive logic gates' [patent_app_type] => 1 [patent_app_number] => 8/904244 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3302 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764085.pdf [firstpage_image] =>[orig_patent_app_number] => 904244 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904244
Method and apparatus for sharing a fet between a plurality of operationally exclusive logic gates Jul 30, 1997 Issued
Array ( [id] => 3885869 [patent_doc_number] => RE036443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Dialer with internal option select circuit programmed with externally hardwired address' [patent_app_type] => 2 [patent_app_number] => 8/903528 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6215 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036443.pdf [firstpage_image] =>[orig_patent_app_number] => 903528 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903528
Dialer with internal option select circuit programmed with externally hardwired address Jul 29, 1997 Issued
Array ( [id] => 3942729 [patent_doc_number] => 05929653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor integrated circuit having programmable enabling circuit' [patent_app_type] => 1 [patent_app_number] => 8/903159 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7486 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929653.pdf [firstpage_image] =>[orig_patent_app_number] => 903159 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903159
Semiconductor integrated circuit having programmable enabling circuit Jul 29, 1997 Issued
Array ( [id] => 4224973 [patent_doc_number] => 06087847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Impedance control circuit' [patent_app_type] => 1 [patent_app_number] => 8/902345 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4616 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087847.pdf [firstpage_image] =>[orig_patent_app_number] => 902345 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902345
Impedance control circuit Jul 28, 1997 Issued
Array ( [id] => 4011278 [patent_doc_number] => 05859542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Programmable logic array integrated circuits with enhanced cascade' [patent_app_type] => 1 [patent_app_number] => 8/898541 [patent_app_country] => US [patent_app_date] => 1997-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4853 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859542.pdf [firstpage_image] =>[orig_patent_app_number] => 898541 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/898541
Programmable logic array integrated circuits with enhanced cascade Jul 21, 1997 Issued
Array ( [id] => 4092682 [patent_doc_number] => 06018250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Programming method to enable system recovery after power failure' [patent_app_type] => 1 [patent_app_number] => 8/884363 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1975 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018250.pdf [firstpage_image] =>[orig_patent_app_number] => 884363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884363
Programming method to enable system recovery after power failure Jun 25, 1997 Issued
Array ( [id] => 4005270 [patent_doc_number] => 05986475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Apparatus and method for resetting a dynamic logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/883195 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3049 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986475.pdf [firstpage_image] =>[orig_patent_app_number] => 883195 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883195
Apparatus and method for resetting a dynamic logic circuit Jun 25, 1997 Issued
Array ( [id] => 4229388 [patent_doc_number] => 06011410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method of charging a dynamic node' [patent_app_type] => 1 [patent_app_number] => 8/883198 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3049 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011410.pdf [firstpage_image] =>[orig_patent_app_number] => 883198 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883198
Method of charging a dynamic node Jun 25, 1997 Issued
Array ( [id] => 3956555 [patent_doc_number] => 05955894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method for controlling the impedance of a driver circuit' [patent_app_type] => 1 [patent_app_number] => 8/881940 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5831 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/955/05955894.pdf [firstpage_image] =>[orig_patent_app_number] => 881940 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881940
Method for controlling the impedance of a driver circuit Jun 24, 1997 Issued
Array ( [id] => 3940991 [patent_doc_number] => 05939898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Input isolation for self-resetting CMOS macros' [patent_app_type] => 1 [patent_app_number] => 8/881265 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2977 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939898.pdf [firstpage_image] =>[orig_patent_app_number] => 881265 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881265
Input isolation for self-resetting CMOS macros Jun 23, 1997 Issued
Menu