Lindsay M Maguire
Examiner (ID: 2393, Phone: (571)272-6039 , Office: P/3693 )
Most Active Art Unit | 3693 |
Art Unit(s) | 3693, 3695, 3692, 3619, 3634 |
Total Applications | 797 |
Issued Applications | 386 |
Pending Applications | 54 |
Abandoned Applications | 319 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3963051
[patent_doc_number] => 05936424
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'High speed bus with tree structure for selecting bus driver'
[patent_app_type] => 1
[patent_app_number] => 8/950380
[patent_app_country] => US
[patent_app_date] => 1997-10-14
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[pdf_file] => patents/05/936/05936424.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/950380 | High speed bus with tree structure for selecting bus driver | Oct 13, 1997 | Issued |
Array
(
[id] => 4032357
[patent_doc_number] => 05883525
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-16
[patent_title] => 'FPGA architecture with repeatable titles including routing matrices and logic matrices'
[patent_app_type] => 1
[patent_app_number] => 8/943890
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[patent_app_date] => 1997-10-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/943890 | FPGA architecture with repeatable titles including routing matrices and logic matrices | Oct 2, 1997 | Issued |
Array
(
[id] => 3991746
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[patent_issue_date] => 1999-09-28
[patent_title] => 'High speed dynamic differential logic circuit employing capacitance matching devices'
[patent_app_type] => 1
[patent_app_number] => 8/938250
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[patent_app_date] => 1997-09-26
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Array
(
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[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Accommodating components'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/928160 | Accommodating components | Sep 11, 1997 | Issued |
Array
(
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[patent_issue_date] => 2000-01-04
[patent_title] => 'CMOS logic circuit with reduced circuit area'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/926450 | CMOS logic circuit with reduced circuit area | Sep 9, 1997 | Issued |
Array
(
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[patent_issue_date] => 1999-12-21
[patent_title] => '5V tolerant PCI I/O buffer on 2.5V technology'
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Array
(
[id] => 4019451
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[patent_title] => 'Chip level bias for buffers driving voltages greater than transistor tolerance'
[patent_app_type] => 1
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Array
(
[id] => 4121830
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[patent_issue_date] => 2000-04-04
[patent_title] => 'Logic circuit controlled by a plurality of clock signals'
[patent_app_type] => 1
[patent_app_number] => 8/911106
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/911106 | Logic circuit controlled by a plurality of clock signals | Aug 12, 1997 | Issued |
Array
(
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[patent_title] => 'Output buffer with regulated voltage biasing for driving voltages greater than transistor tolerance'
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Array
(
[id] => 4214041
[patent_doc_number] => 06028449
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[patent_issue_date] => 2000-02-22
[patent_title] => 'Integrated circuit I/O buffer having pull-up to voltages greater than transistor tolerance'
[patent_app_type] => 1
[patent_app_number] => 8/906343
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Array
(
[id] => 3881517
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[patent_issue_date] => 1998-06-09
[patent_title] => 'Method and apparatus for sharing a fet between a plurality of operationally exclusive logic gates'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/904244 | Method and apparatus for sharing a fet between a plurality of operationally exclusive logic gates | Jul 30, 1997 | Issued |
Array
(
[id] => 3885869
[patent_doc_number] => RE036443
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[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Dialer with internal option select circuit programmed with externally hardwired address'
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Array
(
[id] => 3942729
[patent_doc_number] => 05929653
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[patent_title] => 'Semiconductor integrated circuit having programmable enabling circuit'
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Array
(
[id] => 4224973
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Array
(
[id] => 4011278
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Array
(
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881265 | Input isolation for self-resetting CMOS macros | Jun 23, 1997 | Issued |