Search

Lindsay M Maguire

Examiner (ID: 2393, Phone: (571)272-6039 , Office: P/3693 )

Most Active Art Unit
3693
Art Unit(s)
3693, 3695, 3692, 3619, 3634
Total Applications
797
Issued Applications
386
Pending Applications
54
Abandoned Applications
319

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3639560 [patent_doc_number] => 05631577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Synchronous dual port RAM' [patent_app_type] => 1 [patent_app_number] => 8/668276 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5211 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631577.pdf [firstpage_image] =>[orig_patent_app_number] => 668276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668276
Synchronous dual port RAM Jun 20, 1996 Issued
Array ( [id] => 3749839 [patent_doc_number] => 05801546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Interconnect architecture for field programmable gate array using variable length conductors' [patent_app_type] => 1 [patent_app_number] => 8/667571 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 12499 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801546.pdf [firstpage_image] =>[orig_patent_app_number] => 667571 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/667571
Interconnect architecture for field programmable gate array using variable length conductors Jun 20, 1996 Issued
Array ( [id] => 3905740 [patent_doc_number] => 05751167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'CMOS output buffer circuit which converts CMOS logic signals to ECL logic signals and which discharges parasitic load capacitances' [patent_app_type] => 1 [patent_app_number] => 8/667870 [patent_app_country] => US [patent_app_date] => 1996-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2040 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751167.pdf [firstpage_image] =>[orig_patent_app_number] => 667870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/667870
CMOS output buffer circuit which converts CMOS logic signals to ECL logic signals and which discharges parasitic load capacitances Jun 19, 1996 Issued
Array ( [id] => 3836929 [patent_doc_number] => 05760609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Clock signal providing circuit with enable and a pulse generator with enable for use in a block clock circuit of a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/666193 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 10475 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760609.pdf [firstpage_image] =>[orig_patent_app_number] => 666193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/666193
Clock signal providing circuit with enable and a pulse generator with enable for use in a block clock circuit of a programmable logic device Jun 18, 1996 Issued
Array ( [id] => 4058950 [patent_doc_number] => 05933021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Noise suppression method and circuits for sensitive circuits' [patent_app_type] => 1 [patent_app_number] => 8/665782 [patent_app_country] => US [patent_app_date] => 1996-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4104 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933021.pdf [firstpage_image] =>[orig_patent_app_number] => 665782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665782
Noise suppression method and circuits for sensitive circuits Jun 17, 1996 Issued
Array ( [id] => 4050017 [patent_doc_number] => 05874838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'High voltage-tolerant low voltage input/output cell' [patent_app_type] => 1 [patent_app_number] => 8/664061 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3916 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874838.pdf [firstpage_image] =>[orig_patent_app_number] => 664061 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664061
High voltage-tolerant low voltage input/output cell Jun 12, 1996 Issued
Array ( [id] => 3965879 [patent_doc_number] => 05900746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Ultra low jitter differential to fullswing BiCMOS comparator with equal rise/fall time and complementary outputs' [patent_app_type] => 1 [patent_app_number] => 8/664095 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 71 [patent_no_of_words] => 3536 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900746.pdf [firstpage_image] =>[orig_patent_app_number] => 664095 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664095
Ultra low jitter differential to fullswing BiCMOS comparator with equal rise/fall time and complementary outputs Jun 12, 1996 Issued
Array ( [id] => 3881489 [patent_doc_number] => 05764083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Pipelined clock distribution for self resetting CMOS circuits' [patent_app_type] => 1 [patent_app_number] => 8/664966 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2516 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764083.pdf [firstpage_image] =>[orig_patent_app_number] => 664966 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664966
Pipelined clock distribution for self resetting CMOS circuits Jun 9, 1996 Issued
Array ( [id] => 3894335 [patent_doc_number] => 05723984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Field programmable gate array (FPGA) with interconnect encoding' [patent_app_type] => 1 [patent_app_number] => 8/659279 [patent_app_country] => US [patent_app_date] => 1996-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2247 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/723/05723984.pdf [firstpage_image] =>[orig_patent_app_number] => 659279 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/659279
Field programmable gate array (FPGA) with interconnect encoding Jun 5, 1996 Issued
Array ( [id] => 3859592 [patent_doc_number] => 05767698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'High speed differential output driver with common reference' [patent_app_type] => 1 [patent_app_number] => 8/659293 [patent_app_country] => US [patent_app_date] => 1996-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5756 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767698.pdf [firstpage_image] =>[orig_patent_app_number] => 659293 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/659293
High speed differential output driver with common reference Jun 5, 1996 Issued
Array ( [id] => 3767023 [patent_doc_number] => 05742181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'FPGA with hierarchical interconnect structure and hyperlinks' [patent_app_type] => 1 [patent_app_number] => 8/657990 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7238 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742181.pdf [firstpage_image] =>[orig_patent_app_number] => 657990 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657990
FPGA with hierarchical interconnect structure and hyperlinks Jun 3, 1996 Issued
Array ( [id] => 3836858 [patent_doc_number] => 05760604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Interconnect architecture for field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/656752 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 12501 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760604.pdf [firstpage_image] =>[orig_patent_app_number] => 656752 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656752
Interconnect architecture for field programmable gate array Jun 2, 1996 Issued
Array ( [id] => 3876285 [patent_doc_number] => 05838166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Compact and high-speed judging circuit using misfets' [patent_app_type] => 1 [patent_app_number] => 8/657768 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7679 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838166.pdf [firstpage_image] =>[orig_patent_app_number] => 657768 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657768
Compact and high-speed judging circuit using misfets May 30, 1996 Issued
Array ( [id] => 3866913 [patent_doc_number] => 05793222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Input circuit' [patent_app_type] => 1 [patent_app_number] => 8/654204 [patent_app_country] => US [patent_app_date] => 1996-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9867 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793222.pdf [firstpage_image] =>[orig_patent_app_number] => 654204 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/654204
Input circuit May 27, 1996 Issued
Array ( [id] => 3699941 [patent_doc_number] => 05680064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Level converter for CMOS 3V to from 5V' [patent_app_type] => 1 [patent_app_number] => 8/653973 [patent_app_country] => US [patent_app_date] => 1996-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 132 [patent_no_of_words] => 47850 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680064.pdf [firstpage_image] =>[orig_patent_app_number] => 653973 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653973
Level converter for CMOS 3V to from 5V May 27, 1996 Issued
Array ( [id] => 4015109 [patent_doc_number] => 05889417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Apparatus and method for improving the noise immunity of a dynamic logic signal repeater' [patent_app_type] => 1 [patent_app_number] => 8/653381 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889417.pdf [firstpage_image] =>[orig_patent_app_number] => 653381 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653381
Apparatus and method for improving the noise immunity of a dynamic logic signal repeater May 23, 1996 Issued
Array ( [id] => 3822883 [patent_doc_number] => 05789939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/653186 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 19659 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789939.pdf [firstpage_image] =>[orig_patent_app_number] => 653186 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653186
Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device May 23, 1996 Issued
Array ( [id] => 3737434 [patent_doc_number] => 05694057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'System for enhanced drive in programmable gate arrays' [patent_app_type] => 1 [patent_app_number] => 8/644382 [patent_app_country] => US [patent_app_date] => 1996-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3659 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694057.pdf [firstpage_image] =>[orig_patent_app_number] => 644382 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/644382
System for enhanced drive in programmable gate arrays May 9, 1996 Issued
Array ( [id] => 3775506 [patent_doc_number] => 05734271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Wideband power driver with separate setting delays of leading and trailing edges' [patent_app_type] => 1 [patent_app_number] => 8/639992 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5052 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734271.pdf [firstpage_image] =>[orig_patent_app_number] => 639992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/639992
Wideband power driver with separate setting delays of leading and trailing edges Apr 25, 1996 Issued
Array ( [id] => 3796420 [patent_doc_number] => 05841298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Locally asynchronous, pipeline-able logic circuits for true-single-phase synchronous logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/637468 [patent_app_country] => US [patent_app_date] => 1996-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 13931 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841298.pdf [firstpage_image] =>[orig_patent_app_number] => 637468 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/637468
Locally asynchronous, pipeline-able logic circuits for true-single-phase synchronous logic circuit Apr 24, 1996 Issued
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