Lindsay M Maguire
Examiner (ID: 2393, Phone: (571)272-6039 , Office: P/3693 )
Most Active Art Unit | 3693 |
Art Unit(s) | 3693, 3695, 3692, 3619, 3634 |
Total Applications | 797 |
Issued Applications | 386 |
Pending Applications | 54 |
Abandoned Applications | 319 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3639560
[patent_doc_number] => 05631577
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'Synchronous dual port RAM'
[patent_app_type] => 1
[patent_app_number] => 8/668276
[patent_app_country] => US
[patent_app_date] => 1996-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5211
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[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/631/05631577.pdf
[firstpage_image] =>[orig_patent_app_number] => 668276
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/668276 | Synchronous dual port RAM | Jun 20, 1996 | Issued |
Array
(
[id] => 3749839
[patent_doc_number] => 05801546
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Interconnect architecture for field programmable gate array using variable length conductors'
[patent_app_type] => 1
[patent_app_number] => 8/667571
[patent_app_country] => US
[patent_app_date] => 1996-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
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[patent_no_of_words] => 12499
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/801/05801546.pdf
[firstpage_image] =>[orig_patent_app_number] => 667571
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/667571 | Interconnect architecture for field programmable gate array using variable length conductors | Jun 20, 1996 | Issued |
Array
(
[id] => 3905740
[patent_doc_number] => 05751167
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'CMOS output buffer circuit which converts CMOS logic signals to ECL logic signals and which discharges parasitic load capacitances'
[patent_app_type] => 1
[patent_app_number] => 8/667870
[patent_app_country] => US
[patent_app_date] => 1996-06-20
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[pdf_file] => patents/05/751/05751167.pdf
[firstpage_image] =>[orig_patent_app_number] => 667870
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/667870 | CMOS output buffer circuit which converts CMOS logic signals to ECL logic signals and which discharges parasitic load capacitances | Jun 19, 1996 | Issued |
Array
(
[id] => 3836929
[patent_doc_number] => 05760609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Clock signal providing circuit with enable and a pulse generator with enable for use in a block clock circuit of a programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/666193
[patent_app_country] => US
[patent_app_date] => 1996-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
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[patent_no_of_words] => 10475
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[pdf_file] => patents/05/760/05760609.pdf
[firstpage_image] =>[orig_patent_app_number] => 666193
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/666193 | Clock signal providing circuit with enable and a pulse generator with enable for use in a block clock circuit of a programmable logic device | Jun 18, 1996 | Issued |
Array
(
[id] => 4058950
[patent_doc_number] => 05933021
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'Noise suppression method and circuits for sensitive circuits'
[patent_app_type] => 1
[patent_app_number] => 8/665782
[patent_app_country] => US
[patent_app_date] => 1996-06-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/933/05933021.pdf
[firstpage_image] =>[orig_patent_app_number] => 665782
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/665782 | Noise suppression method and circuits for sensitive circuits | Jun 17, 1996 | Issued |
Array
(
[id] => 4050017
[patent_doc_number] => 05874838
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'High voltage-tolerant low voltage input/output cell'
[patent_app_type] => 1
[patent_app_number] => 8/664061
[patent_app_country] => US
[patent_app_date] => 1996-06-13
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[pdf_file] => patents/05/874/05874838.pdf
[firstpage_image] =>[orig_patent_app_number] => 664061
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/664061 | High voltage-tolerant low voltage input/output cell | Jun 12, 1996 | Issued |
Array
(
[id] => 3965879
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[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Ultra low jitter differential to fullswing BiCMOS comparator with equal rise/fall time and complementary outputs'
[patent_app_type] => 1
[patent_app_number] => 8/664095
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 3536
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[pdf_file] => patents/05/900/05900746.pdf
[firstpage_image] =>[orig_patent_app_number] => 664095
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/664095 | Ultra low jitter differential to fullswing BiCMOS comparator with equal rise/fall time and complementary outputs | Jun 12, 1996 | Issued |
Array
(
[id] => 3881489
[patent_doc_number] => 05764083
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Pipelined clock distribution for self resetting CMOS circuits'
[patent_app_type] => 1
[patent_app_number] => 8/664966
[patent_app_country] => US
[patent_app_date] => 1996-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2516
[patent_no_of_claims] => 12
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[pdf_file] => patents/05/764/05764083.pdf
[firstpage_image] =>[orig_patent_app_number] => 664966
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/664966 | Pipelined clock distribution for self resetting CMOS circuits | Jun 9, 1996 | Issued |
Array
(
[id] => 3894335
[patent_doc_number] => 05723984
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Field programmable gate array (FPGA) with interconnect encoding'
[patent_app_type] => 1
[patent_app_number] => 8/659279
[patent_app_country] => US
[patent_app_date] => 1996-06-06
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[pdf_file] => patents/05/723/05723984.pdf
[firstpage_image] =>[orig_patent_app_number] => 659279
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/659279 | Field programmable gate array (FPGA) with interconnect encoding | Jun 5, 1996 | Issued |
Array
(
[id] => 3859592
[patent_doc_number] => 05767698
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'High speed differential output driver with common reference'
[patent_app_type] => 1
[patent_app_number] => 8/659293
[patent_app_country] => US
[patent_app_date] => 1996-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/767/05767698.pdf
[firstpage_image] =>[orig_patent_app_number] => 659293
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/659293 | High speed differential output driver with common reference | Jun 5, 1996 | Issued |
Array
(
[id] => 3767023
[patent_doc_number] => 05742181
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'FPGA with hierarchical interconnect structure and hyperlinks'
[patent_app_type] => 1
[patent_app_number] => 8/657990
[patent_app_country] => US
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[pdf_file] => patents/05/742/05742181.pdf
[firstpage_image] =>[orig_patent_app_number] => 657990
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/657990 | FPGA with hierarchical interconnect structure and hyperlinks | Jun 3, 1996 | Issued |
Array
(
[id] => 3836858
[patent_doc_number] => 05760604
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Interconnect architecture for field programmable gate array'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 656752
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Array
(
[id] => 3876285
[patent_doc_number] => 05838166
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[patent_issue_date] => 1998-11-17
[patent_title] => 'Compact and high-speed judging circuit using misfets'
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[pdf_file] => patents/05/838/05838166.pdf
[firstpage_image] =>[orig_patent_app_number] => 657768
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/657768 | Compact and high-speed judging circuit using misfets | May 30, 1996 | Issued |
Array
(
[id] => 3866913
[patent_doc_number] => 05793222
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[patent_issue_date] => 1998-08-11
[patent_title] => 'Input circuit'
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[pdf_file] => patents/05/793/05793222.pdf
[firstpage_image] =>[orig_patent_app_number] => 654204
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/654204 | Input circuit | May 27, 1996 | Issued |
Array
(
[id] => 3699941
[patent_doc_number] => 05680064
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[patent_kind] => NA
[patent_issue_date] => 1997-10-21
[patent_title] => 'Level converter for CMOS 3V to from 5V'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/653973 | Level converter for CMOS 3V to from 5V | May 27, 1996 | Issued |
Array
(
[id] => 4015109
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[patent_issue_date] => 1999-03-30
[patent_title] => 'Apparatus and method for improving the noise immunity of a dynamic logic signal repeater'
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[firstpage_image] =>[orig_patent_app_number] => 653381
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/653381 | Apparatus and method for improving the noise immunity of a dynamic logic signal repeater | May 23, 1996 | Issued |
Array
(
[id] => 3822883
[patent_doc_number] => 05789939
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[patent_title] => 'Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device'
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Array
(
[id] => 3737434
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/637468 | Locally asynchronous, pipeline-able logic circuits for true-single-phase synchronous logic circuit | Apr 24, 1996 | Issued |